LTC1436AIGN-PLL Linear Technology, LTC1436AIGN-PLL Datasheet - Page 23
![IC SW REG SYNC STEP-DOWN 24-SSOP](/photos/6/59/65961/161-24-ssop_sml.jpg)
LTC1436AIGN-PLL
Manufacturer Part Number
LTC1436AIGN-PLL
Description
IC SW REG SYNC STEP-DOWN 24-SSOP
Manufacturer
Linear Technology
Type
Step-Down (Buck)r
Datasheet
1.LTC1436AIGN-PLLPBF.pdf
(28 pages)
Specifications of LTC1436AIGN-PLL
Internal Switch(s)
No
Synchronous Rectifier
Yes
Number Of Outputs
1
Voltage - Output
1.19 ~ 9 V
Current - Output
50mA
Frequency - Switching
125kHz ~ 240kHz
Voltage - Input
3.5 ~ 30 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power - Output
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTC1436AIGN-PLL
Manufacturer:
Linear Technology
Quantity:
135
Part Number:
LTC1436AIGN-PLL
Manufacturer:
LT/凌特
Quantity:
20 000
Part Number:
LTC1436AIGN-PLL#PBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
APPLICATIONS
The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Siliconix Si4412DY results
in: R
voltage with T (estimated) = 50°C:
The most stringent requirement for the synchronous
N-channel MOSFET occurs when V
circuit). In this case the worst-case dissipation rises to:
With the 0.033Ω sense resistor I
increasing the Si4412DY dissipation to 950mW at a die
temperature of 105°C.
C
temperature. C
output ripple. The output ripple in continuous mode will be
highest at the maximum input voltage. The output voltage
ripple due to ESR is approximately:
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1436A/LTC1437A. These items are also illustrated
graphically in the layout diagram of Figure 15. Check the
following in your layout:
1. Are the signal and power grounds segregated? The
P
IN
MAIN
LTC1436A/LTC1437A signal ground pin must return to
the (–) plate of C
P
V
is chosen for an RMS current rating of at least 1.5A at
SYNC
ORIPPLE
DS(ON)
=
+
= ⎡
1 6
2 5 22
22
.
.
= 0.042Ω, C
⎣ ⎢
I
V
V
=
(
SC AVG
( )
OUT
R
( )
3 1
V
ESR
2
) ( )(
is chosen with an ESR of 0.03Ω for low
1 85
OUT
[
U
.
⎤
⎦ ⎥
( )
+
2
∆
( )
. The power ground connects to the
3
(
1 δ
I
L
0 005 50
RSS
A
+
INFORMATION
.
U
=
100
= 100pF. At maximum input
0 03
R
.
)
DS ON
(
pF
( )
SC(AVG)
Ω
)(
° −
W
C
(
250
1 3
OUT
.
25
A
kHz
= 4A will result,
)
= 0 (i.e. short
°
=
C
)
39
)
=
]
(
U
88
mV
0 042
.
mW
P- P
Ω
)
2. Does the LTC1436A/LTC1437A V
3. Are the SENSE
4. Does the (+) plate of C
5. Is the INTV
6. Keep the switching node SW away from sensitive small-
7. Route the PLLIN line away from Boost and SW pins to
8. SGND should be used exclusively for grounding exter-
9. If operating close to the minimum on-time limit, is the
source of the bottom N-channel MOSFET, anode of the
Schottky diode, and (–) plate of C
as short lead lengths as possible.
the (+) plate of C
resistive divider R1/R2 must be connected between the
(+) plate of C
tor should be as close as possible to the LTC1436A/
LTC1437A.
minimum PC trace spacing? The filter capacitor be-
tween SENSE
possible to the LTC1436A/LTC1437A.
topside MOSFET(s) as closely as possible? This capaci-
tor provides the AC current to the MOSFET(s).
between INTV
pacitor carries the MOSFET driver peak currents.
signal nodes. Ideally, the switch node should be placed
at the furthest point from the LTC1436A/LTC1437A.
avoid unwanted pickup (Boost and SW pins have high
dV/dTs).
nal components on PLL LPF, C
V
sense resistor oriented on the radial axis of the induc-
tor? See Figure 13.
OSENSE
and AUXFB pins.
LTC1436A-PLL/LTC1437A
CC
OUT
CC
+
decoupling capacitor connected closely
–
and SENSE
and SENSE
and signal ground. The 100pF capaci-
and the power ground pin? This ca-
OUT
? In adjustable applications, the
IN
connect to the drain of the
+
–
leads routed together with
should be as close as
IN
OSENSE
OSC
, which should have
LTC1436A
, I
pin connect to
TH
, LBI, SFB,
23
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