LT3434IFE#TR Linear Technology, LT3434IFE#TR Datasheet - Page 20

• Manufacturer Part Number: LT3434IFE#TR
• Description: IC REG SW BUCK 3A 200KHZ 16TSSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LT3434IFE#TR

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1.25 ~ 54 V
• Current - Output: 3A
• Frequency - Switching: 200kHz
• Voltage - Input: 3.3 ~ 60 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP Exposed Pad, 16-eTSSOP, 16-HTSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

LT3434
APPLICATIO S I FOR ATIO
LT3434 switch. When operating at higher currents and
input voltages, with poor layout, this spike can generate
voltages across the LT3434 that may exceed its absolute
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
The V
possible from the switch and boost nodes. The LT3434
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.
20
GND
C
V
C1
OUT
GND
and FB components should be kept as far away as
C3
+
V
MINIMIZE
IN
D1-C3
LOOP
Figure 11. High Speed Switching Path
C2
V
IN
4
C2
D1
L1
Figure 12. Suggested Layout
C4
V
IN
D2
U
CIRCULATION
LT3434
FREQUENCY
1
2
3
4
5
6
7
8
PATH
PLACE VIA's UNDER EXPOSED
HIGH
PAD TO A BOTTOM PLANE TO
CONNECT PIN 8 GND TO THE
PIN 17 EXPOSED PAD GND
NC
SW
V
V
SW
BOOST
C
GND
IN
IN
T
SW
ENHANCE THERMAL
U
LT3434
CONDUCTIVITY
2
PGOOD
SHDN
SYNC
PGFB
BIAS
C
V
FB
SS
D1
C
W
L1
16
15
14
13
12
11
10
9
C5
C1
3434 F11
R3
R1
R2
C2
FROM BIAS TRACE
KEEP SEPARATE
LOAD
KELVIN SENSE
V
TRACE AND
U
OUT
FEEDBACK
3434 F12
Board layout also has a significant effect on thermal
resistance. Pin 8 and the exposed die pad, Pin 17, are a
continuous copper plate that runs under the LT3434 die.
This is the best thermal path for heat out of the package.
Reducing the thermal resistance from Pin 8 and exposed
pad onto the board will reduce die temperature and in-
crease the power capability of the LT3434. This is achieved
by providing as much copper area as possible around the
exposed pad. Adding multiple solder filled feedthroughs
under and around this pad to an internal ground plane will
also help. Similar treatment to the catch diode and coil
terminations will reduce any additional heating effects.
THERMAL CALCULATIONS
Power dissipation in the LT3434 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
Switch loss:
Boost current loss:
Quiescent current loss:
R
t
(t
t
t
t
f = switch frequency
EFF
r
f
IR
SW
r
= (V
= (V
P
P
P
+ t
= t
SW
BOOST
= effective switch current/voltage overlap time
Q
f
= switch resistance (≈0.15 when hot )
IF
= V
IN
IN
+ t
=
/1.7)ns
= (I
/1.2)ns
IN
IR
R
=
OUT
SW OUT
(0.0026) + V
+ t
(
V
OUT
IF
(
/0.2)ns
I
)
) (
V
2
V
IN
IN
) (
I
2
OUT
V
OUT
OUT
/
40
)
)
(0.001)
+
t
EFF
( )(
1 2 /
I
OUT
)( )( )
V
IN
3434fb
f