LT1765EFE-5 Linear Technology, LT1765EFE-5 Datasheet - Page 11

• Manufacturer Part Number: LT1765EFE-5
• Description: IC REG SW STEPDOWN 3A 16-TSSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LT1765EFE-5

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 5V
• Current - Output: 3A
• Frequency - Switching: 1.25MHz
• Voltage - Input: 3 ~ 25 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP Exposed Pad, 16-eTSSOP, 16-HTSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

APPLICATIONS INFORMATION
An internal comparator will force the part into shutdown
below the minimum V
to prevent excessive discharge of battery-operated sys-
tems. If an adjustable UVLO threshold is required, the
shutdown pin can be used. The threshold voltage of the
shutdown pin comparator is 1.33V. A 3μA internal current
source defaults the open pin condition to be operating (see
Typical Performance Graphs). Current hysteresis is added
above the SHDN threshold. This can be used to set voltage
hysteresis of the UVLO using the following:
Example: switching should not start until the input is above
4.75V and is to stop if the input falls below 3.75V.
Keep the connections from the resistors to the SHDN
pin short and make sure that the interplane or surface
capacitance to the switching nodes are minimized. If high
resistor values are used, the SHDN pin should be bypassed
with a 1nF capacitor to prevent coupling problems from
the switch node.
SYNCHRONIZATION
The SYNC pin is used to synchronize the internal oscilla-
tor to an external signal. The SYNC input must pass from
a logic level low, through the maximum synchronization
V
V
V
V
R
R
R
R
H
L
H
L
1
1
2
2
=
– Turn-off threshold
= 3.75V
=
– Turn-on threshold
= 4.75V
=
=
V
4 75
(
(
H
7
.
V
4 75
μ
−
H
.
A
−
V
V
7
R
L
V
1 33
143
μ
−
1 33
1
.
A
−
.
3 75
1 33
.
1 33
k
.
V
.
V
)
V
IN
V
+ μ
V
=
3
of 2.6V. This feature can be used
)
143
+ μ
A
3
k
A
=
49 4
.
k
threshold with a duty cycle between 20% and 80%. The
input can be driven directly from a logic level output. The
synchronizing range is equal to initial operating frequency
up to 2MHz. This means that minimum practical sync
frequency is equal to the worst-case high self-oscillating
frequency (1.6MHz), not the typical operating frequency
of 1.25MHz. Caution should be used when synchronizing
above 1.8MHz because at higher sync frequencies the
amplitude of the internal slope compensation used to
prevent subharmonic switching is reduced. This type of
subharmonic switching only occurs at input voltages less
than twice output voltage. Higher inductor values will tend
to eliminate this problem. See Frequency Compensation
section for a discussion of an entirely different cause of
subharmonic switching before assuming that the cause is
insuffi cient slope compensation. Application Note 19 has
more details on the theory of slope compensation.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
effi ciency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. Shortening
this path will also reduce the parasitic trace inductance
of approximately 25nH/inch. At switch off, this parasitic
inductance produces a fl yback spike across the LT1765
switch. When operating at higher currents and input volt-
ages, with poor layout, this spike can generate voltages
across the LT1765 that may exceed its absolute maximum
LT1765/LT1765-1.8/LT1765-2.5/
V
IN
C3
Figure 5. High Speed Switching Path
V
IN
CIRCULATING
FREQUENCY
LT1765-3.3/LT1765-5
LT1765
HIGH
PATH
SW
D1 C1
L1
LOAD
11
1765 F05
5V
1765fd