LTC1709EG-85 Linear Technology, LTC1709EG-85 Datasheet - Page 19

• Manufacturer Part Number: LTC1709EG-85
• Description: IC SW REG SYNC STEP-DWN 36-SSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC1709EG-85

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 1.3 ~ 3.5 V
• Current - Output: 3A
• Voltage - Input: 4 ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -
• Frequency - Switching: -
• Other names: LTC1709EG85

APPLICATIO S I FOR ATIO
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, f
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin. A simplified block
diagram is shown in Figure 6.
If the external frequency (f
lator frequency f
pulling up the PLLFLTR pin. When the external frequency
is less than f
down the PLLFLTR pin. If the external and internal fre-
quencies are the same but exhibit a phase difference, the
current sources turn on for an amount of time correspond-
ing to the phase difference. Thus the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point the phase comparator output is
open and the filter capacitor C
LTC1709-85 PLLIN pin must be driven from a low imped-
ance source such as a logic gate located close to the pin.
The loop filter components (C
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C
acquires lock. Typically R
0.1 F.
f
H
= f
H
, is equal to the capture range, f
C
= 0.5 f
0SC
LP
, current is sunk continuously, pulling
0SC
and R
U
, current is sourced continuously,
O
(150kHz-300kHz)
LP
U
PLLIN
LP
PLLIN
determine how fast the loop
EXTERNAL
=10k and C
OSC
LP
) is greater than the oscil-
LP
, R
holds the voltage. The
W
LP
50k
) smooth out the
Figure 6. Phase-Locked Loop Block Diagram
LP
C:
is 0.01 F to
FREQUENCY
DETECTOR
DETECTOR
DIGITAL
PHASE/
PHASE
U
2.4V
Minimum On-Time Considerations
Minimum on-time, t
that the LTC1709-85 is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1709-85 will begin to skip
cycles resulting in variable frequency operation. The out-
put voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.
The minimum on-time for the LTC1709-85 is generally
less than 200ns. However, as the peak sense voltage
decreases, the minimum on-time gradually increases.
This is of particular concern in forced continuous applica-
tions with low ripple current at light loads. If the duty cycle
drops below the minimum on-time limit in this situation,
a significant amount of cycle skipping can occur with
correspondingly larger ripple current and voltage ripple.
If an application can operate close to the minimum
on-time limit, an inductor must be chosen that has a low
enough inductance to provide sufficient ripple amplitude
to meet the minimum on-time requirement. As a general
rule, keep the inductor ripple current of each phase equal
to or greater than 15% of I
t
ON MIN
PLLFLTR
R
10k
V f
LP
V
IN
OUT
ON(MIN)
C
LP
OSC
170985 F07
, is the smallest time duration
OUT(MAX)
LTC1709-85
at V
IN(MAX)
.
19
170985f