MAX5093BATE+T Maxim Integrated Products, MAX5093BATE+T Datasheet - Page 9
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MAX5093BATE+T
Manufacturer Part Number
MAX5093BATE+T
Description
IC REG LDO W/BOOST 16TQFN
Manufacturer
Maxim Integrated Products
Type
Step-Up (Boost)r
Datasheet
1.MAX5092AATE.pdf
(24 pages)
Specifications of MAX5093BATE+T
Internal Switch(s)
Yes
Synchronous Rectifier
No
Number Of Outputs
2
Voltage - Output
5V, 1.5 ~ 10 V
Current - Output
250mA
Voltage - Input
3.5 ~ 72 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-TQFN Exposed Pad
Power - Output
2.67W
Polarity
Positive
Input Voltage Max
72 V
Output Voltage
1.5 V to 10 V, 5 V
Output Type
Adjustable, Fixed
Dropout Voltage (max)
1.6 V at 250 mA
Output Current
250 mA
Line Regulation
1.6 mV / V
Load Regulation
0.2 mV / mA
Voltage Regulation Accuracy
1.5 %
Maximum Power Dissipation
2.666 W
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Reference Voltage
1.235 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Frequency - Switching
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
10, 11
PIN
12
13
14
15
16
—
1
2
3
4
5
6
7
8
9
4V to 72V Input LDOs with Boost Preregulator
OUT_SENSE LDO Regulator Output Sense. Connect OUT_SENSE to OUT at the output capacitor near the load.
PGND_LDO
PGND_BST
BSOUT
RESET
NAME
SGND
HOLD
BSFB
OUT
SET
EN
LX
VL
CT
EP
IN
_______________________________________________________________________________________
Input Supply Voltage. Bypass IN to the power ground plane with a 47µF (low-ESR) aluminum electrolytic
capacitor in parallel with a 1µF ceramic capacitor placed as close to the IC as possible.
Enable Input. Drive EN high to turn on the IC. Drive EN low to disable the IC. Connect EN directly to IN for
always-on operation.
Signal Ground. Connect SGND to the signal ground plane and the exposed paddle. Connect the power
ground and signal ground plane together at the negative terminal of the input capacitor(s).
Output Hold. When HOLD is forced low, the regulator stores the on-state of the output, allowing the
regulator to remain enabled even if EN is pulled low. To shut down the regulator, release HOLD after EN is
pulled low. If HOLD is unused, either connect HOLD to OUT or leave unconnected. HOLD is internally
connected to OUT through a 4µA pullup current.
LDO Power Ground. Connect PGND_LDO to the power ground plane. Connect the PGND_LDO ground and
signal ground plane together.
Feedback Input for the LDO. Connect SET directly to SGND to set the output voltage of the LDO to the
preset voltage of 3.3V (MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B). Connect SET to the center
tap of a resistor-divider connected between the LDO output and SGND to set the output voltage. V
regulates to 1.24V when using an adjustable output.
LDO Regulator Output. Bypass OUT to the power ground plane with a 10µF ceramic capacitor. V
regulates to a preset voltage of 3.3V (MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B), or is
adjustable from 1.5V to 9V (MAX5902_) or 1.5V to 10V (MAX5093_).
Boost Regulator Output Voltage. Bypass BSOUT to the PGND_BST ground plane with a 22µF (low-ESR)
aluminum electrolytic capacitor in parallel with a 1µF ceramic capacitor placed as close to the IC as
possible. Connect BSFB directly to SGND to regulate the BOOST output to a fixed voltage of 7V for V
7V. V
12V (MAX5093_) by connecting BSFB to the center tap of an external resistor-divider connected between
the BOOST output and PGND_BST.
Inductor Connection to the Drain of the Internal Power MOSFET. Connect LX to the switched side of the
inductor. Connect pins 10 and 11 together as close to the device as possible. For the MAX5093, also
connect LX to the anode of the external Schottky diode.
Boost Regulator Power Ground. Connect PGND_BST to the power ground plane. Connect the PGND_BST
ground plane and the signal ground plane together at the negative terminal of the input capacitor(s).
Feedback Input for the Boost Regulator. Connect BSFB directly to SGND to set the boost regulator output
voltage to 7V. Connect BSFB to the center tap of an external resistor-divider connected between BSOUT
and SGND to set the output voltage. V
Internal Regulator Output for IC Supply. Bypass VL to SGND with a 1µF/6.3V ceramic capacitor placed as
close to the IC as possible. V
RESET Timeout Programming Input. Connect a capacitor from CT to SGND to set the RESET timeout
period. See the CT Capacitor Selection section.
RESET Output. RESET is an open-drain output that goes high impedance when V
output voltage threshold after a programmed time delay. RESET pulls low immediately once V
below 90% of the regulated LDO output voltage.
Exposed Paddle. Connect to the signal ground plane (SGND). Connect to a large-signal ground plane for
increased thermal performance.
BSOUT
follows V
IN
for V
BSOUT
VL
regulates to 5.5V with V
- V
OUT
BSFB
> 2.5V (typ). V
regulates to 1.24V when using an adjustable output.
FUNCTION
BSOUT
BSOUT
≥ 5.5V.
is programmable up to 11V (MAX5092_) or
Pin Description
OUT
exceeds 92% of the
OUT
OUT
drops
SET
IN
≤
9