NCP1579DR2G ON Semiconductor, NCP1579DR2G Datasheet - Page 9

• Manufacturer Part Number: NCP1579DR2G
• Description: IC CTLR SYNC BUCK LV 8-SOIC
• Manufacturer: ON Semiconductor
• Type: Step-Down (Buck)r

Specifications of NCP1579DR2G

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: Adjustable
• Current - Output: 1A
• Frequency - Switching: 275kHz
• Voltage - Input: 4.5 ~ 13.2 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Topology: Buck
• Output Current: 1000 mA
• Switching Frequency: 317 KHz
• Duty Cycle (max): 80 %
• Operating Supply Voltage: 5 V, 12 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Synchronous Pin: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

tight output voltage regulation. In contrast, smaller values of
inductance increase the regulator’s maximum achievable
slew rate and decrease the necessary capacitance, at the
expense of higher ripple current. The peak-to-peak ripple
current for NCP1579 is given by the following equation:
where Ipk-pk
From this equation it is clear that the ripple current increases
as L
dynamic response and ripple current.
Feedback and Compensation
to be adjusted from 0.8 V to 5.0 V via an external resistor
divider network. The controller will try to maintain 0.8 V at
the feedback pin. Thus, if a resistor divider circuit was
placed across the feedback pin to V
regulate the output voltage proportional to the resistor
divider network in order to maintain 0.8 V at the FB pin.
The relationship between the resistor divider network above
and the output voltage is shown in the following equation:
efficiency and output voltage accuracy. For high values of
R1 there is less current consumption in the feedback
network, However the trade off is output voltage accuracy
due to the bias current in the error amplifier. The output
voltage error of this bias current can be estimated using the
following equation (neglecting resistor tolerance):
The NCP1579 allows the output of the DC-DC converter
Resistor R1 is selected based on a design tradeoff between
Once R1 has been determined, R2 can be calculated.
OUT
Figure 10. Type II Transconductance Error
C
R
c
c
decreases, emphasizing the trade-off between
Ipk * pk
LOUT
Error% +
R
2
+ R
is the peak to peak current of the output.
LOUT
C
R1
R2
1
p
0.1 mA
V
Amplifier
EA
OUT
+
V
Gm
V
L
REF
OUT
OUT
V
FB
OUT
V
R
* V
REF
V
1
OUT
(1 * D)
ref
275 kHz
REF
100%
, the controller will
+
−
,
R
R
1
2
http://onsemi.com
9
amplifier (EOTA). The compensation network consists of
the internal error amplifier and the impedance networks ZIN
(R
compensation network has to provide a closed loop transfer
function with the highest 0 dB crossing frequency to have
fast response (but always lower than F
gain in DC conditions to minimize the load regulation. A
stable control loop has a gain crossing with -20 dB/decade
slope and a phase margin greater than 45°. Include
worst-case component variations when determining phase
margin. Loop stability is defined by the compensation
network around the EOTA, the output capacitor, output
inductor and the output divider. Figure 11 shows the open
loop and closed loop gain plots.
Compensation Network Frequency:
frequency
frequency,
Thermal Considerations
MOSFETs used, V
average MOSFET gate current typically dominates the
control IC power dissipation. The IC power dissipation is
determined by the formula:
Where:
Figure 10 shows a typical Type II transconductance error
The inductor and capacitor form a double pole at the
The ESR of the output capacitor creates a “zero” at the
The zero of the compensation network is formed as,
The pole of the compensation network is calculated as,
The power dissipation of the NCP1579 varies with the
1
, R
Figure 11. Gain Plot of the Error Amplifier
2
) and external Z
P
IC
+ (I
F
F
ESR
F
CC
LC
p
CC
F
, and the boost voltage (V
Z
+
+
+
+
2p
2p
2p
V
2p
CC
FB
) ) P
R
ESR
1
1
1
L
R
c
(R
1
o
c
C
c
, C
TG
C
c
SW
C
p
C
) P
o
c
/8) and the highest
o
and C
BG
BST
p
). The
). The