KSZ8999 Micrel Inc, KSZ8999 Datasheet
KSZ8999
Specifications of KSZ8999
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KSZ8999 Summary of contents
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KS8999 General Description The KS8999 contains eight 10/100 physical layer transceiv- ers, nine MAC (Media Access Control) units with an inte- grated layer 2 switch. The device runs in two modes. The first mode is an eight port integrated switch ...
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... Industrial temperature range: – +85 C (KSZ8999I) • Available in 208-pin PQFP package KS8999 Ordering Information Part Number Temperature Range KS8999 +70 C KS8999I – +85 C KSZ8999 +70 C KSZ8999I – + Micrel Package 208-Pin PQFP 208-Pin PQFP 208-Pin PQFP 208-Pin PQFP January 2005 ...
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KS8999 Revision History Revision Date Summary of Changes 1.00 11/27/00 Preliminary Release 1.01 03/30/01 Update maximum frame size Update EEPROM priority descriptions Update I/O pin definitionUpdate I/O descriptions Update Electrical Characteristics 1.02 04/20/01 Correct timing information 1.03 05/11/01 Add MDI/MDI-X ...
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KS8999 Table of Contents System Level Applications ......................................................................................................................................... 6 Pin Description ............................................................................................................................................................ 7 I/O Grouping ........................................................................................................................................................... 13 I/O Descriptions ......................................................................................................................................................... 13 Pin Configuration ...................................................................................................................................................... 19 Functional Overview: Physical Layer Transceiver ................................................................................................ 20 100BaseTX Transmit ........................................................................................................................................... 20 100BaseTX Receive ............................................................................................................................................ 20 ...
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KS8999 EEPROM Memory Map .............................................................................................................................................. 29 General Conrol Register .............................................................................................................................. 29 Priority Classification Control: 802.1p Tag Field ......................................................................................... 29 Port 1 Control Register ................................................................................................................................ 29 Port 2 Control Register ................................................................................................................................ 30 Port 3 Control Register ................................................................................................................................ 30 Port 4 Control ...
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KS8999 System Level Applications The KS8999 can be configured to fit either in an eight port 10/ 100 application nine port 10/100 network interface with an extra MII/7-wire port. This MII/7-wire port can be connected to an ...
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KS8999 Pin Description Pin Number Pin Name Type 1 VDD_RX 2 GND_RX GND 3 GND_RX GND 4 VDD_RX 5 RXP[3] 6 RXM[3] 7 AOUT2 8 DOUT2 9 TXP[3] 10 TXM[3] 11 QH[5] Opd 12 QH[4] Opd 13 QH[3] Opd 14 ...
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KS8999 Pin Number Pin Name Type 35 GND-ISO GND 36 VDD_TX 37 VDD_TX 38 GND_TX GND 39 QL[2] Opd 40 QL[3] Opd 41 QL[4] Opd 42 QL[5] Opd 43 TXP[6] 44 TXM[6] 45 DOUT 46 AOUT 47 RXP[6] 48 RXM[6] ...
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KS8999 Pin Number Pin Name Type 70 FXSD[7] 71 FXSD[8] 72 GND_RCV GND 73 GND_RCV GND 74 VDD_RCV 75 VDD_RCV 76 GND_RCV GND 77 GND_RCV GND 78 VDD_RCV 79 VDD_RCV 80 BTOUT2 81 CTOUT2 82 RLPBK 83 MUX[1] 84 MUX[2] ...
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KS8999 Pin Number Pin Name Type 105 VDD-IO 106 GND GND 107 GND GND 108 VDD 109 BIST 110 RST# 111 LED[1][3] Ipu/O 112 LED[1][2] Ipu/O 113 LED[1][1] Ipu/O 114 LED[1][0] Ipu/O 115 LED[2][3] Ipu/O 116 LED[2][2] Ipu/O 117 LED[2][1] ...
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KS8999 Pin Number Pin Name Type 140 LED[5][0] Ipu/O 141 LED[6][3] Ipu/O 142 LED[6][2] Ipu/O 143 LED[6][1] Ipu/O 144 LED[6][0] Ipu/O 145 LED[7][3] Ipu/O 146 LED[7][2] Ipu/O 147 LED[7][1] Ipu/O 148 VDD-IO 149 LED[7][0] Ipu/O 150 LED[8][3] Ipu/O 151 LED[8][2] ...
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KS8999 Pin Number Pin Name Type 175 Reserve 176 X1 177 X2 178 VDD_PLLTX 179 GND_PLLTX GND 180 CTOUT 181 BTOUT 182 VDD_RCV 183 VDD_RCV 184 GND_RCV GND 185 GND_RCV GND 186 VDD_RCV 187 VDD_RCV 188 GND_RCV GND 189 GND_RCV ...
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KS8999 I/O Grouping Group Name Description PHY Physical Interface MII Media Independent Interface SNI Serial Network Interface IND LED Indicators UP Unmanaged Programmable CTRL Control and Miscellaneous TEST Test (Factory) PWR Power and Ground I/O Descriptions Group I/O Names Active ...
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KS8999 Group I/O Names Active Status LED[1:9][1] L LED[1:9][2] L LED[1:9][ MODESEL[3:0] H LED[1][3] LED[1][2] LED[1][1] Note 1. All unmanaged programming takes place at reset time only. For unmanaged programming Float Pull-down ...
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KS8999 Group I/O Names Active Status LED[1][0] LED[2][3] LED[2][2] LED[2][1] LED[2][0] LED[3][3] LED[3][2] LED[3][1] LED[3][0] LED[4][3] LED[4][2] LED[4][1] LED[4][0] LED[5][3] LED[5][2] LED[5][1] LED[5][0] LED[9][3] LED[9][2] Note 1. All unmanaged programming takes place at reset time only. For unmanaged programming: F ...
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KS8999 Group I/O Names Active Status LED[9][1] LED[9][0] LED[6][3] LED[6][2] LED[6][1:0] LED[7][3] LED[7][2] LED[7][1] LED[7][0] LED[8][3] LED[8][2] LED[8][1] LED[8][0] MRXD[3] MRXD[2] MRXD[1] MRXD[0] CTRL EN1P H MIIS[1:0] H Note 1. All unmanaged programming takes place at reset time only. For ...
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KS8999 Group I/O Names Active Status PRSV H CFGMODE H X1 Clock X2 Clock SCL Clock SDA I/O RST# L TEST TESTEN H SCANEN H MUX[1:2] H AOUT H DOUT H AOUT2 H DOUT2 H BTOUT H CTOUT H BTOUT2 ...
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KS8999 Group I/O Names Active Status GND_PLLTX GND-ISO VDD VDD-IO GND KS8999 Description Ground for phase locked loop circuitry Analog ground 2.0V for core digital circuitry 2.0V, 2.5V or 3.3V for I/O circuitry Ground for digital circuitry 18 Micrel January ...
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KS8999 Pin Configuration VDD 157 LED[9][3] LED[9][2] LED[9][1] LED[9][0] MIIS[1] MIIS[0] MODESEL[3] MODESEL[2] MODESEL[1] MODESEL[0] TESTEN SCANEN PRSV CFGMODE T[5] T[4] RESERVE RESERVE X1 X2 VDD_PLLTX GND_PLLTX CTOUT BTOUT VDD_RCV VDD_RCV GND_RCV GND_RCV VDD_RCV VDD_RCV GND_RCV GND_RCV FXSD[1] FXSD[2] FXSD[3] ...
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KS8999 Functional Overview: Physical Layer Transceiver 100BaseTX Transmit The 100BaseTX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ to NRZI conver- sion, MLT3 encoding and transmission. The circuit starts with a parallel to serial conversion, which converts ...
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KS8999 Power Management Power Save Mode The KS8999 will turn off everything except for the Energy Detect and PLL circuits when the cable is not installed on an individual port basis. In other words, the KS8999 will shutdown most of ...
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KS8999 Functional Overview: Switch Core Address Look-Up The internal look-up table stores MAC addresses and their associated information. It contains 1K full CAM with 48-bit address plus switching information. The KS8999 is guaranteed to learn 1K addresses and distinguishes itself ...
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KS8999 Backoff Algorithm The KS8999 implements the IEEE Std 802.3 binary exponential back-off algorithm, and optional “aggressive mode” back off. After 16 collisions, the packet will be optionally dropped depending on the chip configuration. Late Collision If a transmit packet ...
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KS8999 MII Interface Operation The MII (Media Independent Interface) operates in either a MAC or PHY mode. In the MAC mode, the KS8999 MII acts like a MAC and in the PHY mode, it acts like a PHY device. This ...
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KS8999 Note that the signal MRXER is not provided on the MII interface for the KS8999 for PHY mode operation and MTXER is not represented for MAC mode. Normally this would indicate a receive / transmit error coming from the ...
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KS8999 SNI Interface (7-wire) Operation The SNI (Serial Network Interface) is compatible with some controllers used for network layer protocol processing. KS8999 acts like a PHY device to external controllers. This interface can be directly connected to these types of ...
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KS8999 The table below briefly summarizes priority features. For more detailed settings see the EEPROM register description. Register(s) Bit(s) Global/Port 2 3-2 Global 2 1 Global 4-12 0 Port 4-12 5 Port 40-47 7-0 Global 4-12 4 Port 3 7-0 ...
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KS8999 EEPROM Operation The EEPROM interface utilizes 2 pins that provide a clock and a serial data path. As part of the initialization sequence, the KS8999 reads the contents of the EEPROM and loads the values into the appropriate registers. ...
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KS8999 EEPROM Memory Map Address Name 0 7-0 1 7-0 General Control Register 2 7 Priority Classification Control – 802.1p tag field ...
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KS8999 Address Name 4 0 Port 2 Control Register 5 7 Port 3 Control Register 6 7 ...
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KS8999 Address Name Port 5 Control Register 8 7 Port 6 Control Register 9 7 ...
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KS8999 Address Name Port 7 Control Register 10 7 Port 8 Control Register 11 7 Port ...
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KS8999 Address Name Port 1 VLAN Mask Register Port 2 VLAN Mask Register ...
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KS8999 Address Name Port 3 VLAN Mask Register Port 4 VLAN Mask Register ...
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KS8999 Address Name 16 0 Port 5 VLAN Mask Register Port 6 VLAN Mask Register ...
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KS8999 Address Name Port 7 VLAN Mask Register Port 8 VLAN Mask Register ...
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KS8999 Address Name Port 9 VLAN Mask Register Port 1 VLAN Tag Insertion Value Registers 22 7 3-0 23 7-0 Port ...
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KS8999 Address Name Port 5 VLAN Tag Insertion Value Registers 30 7 3-0 31 7-0 Port 6 VLAN Tag Insertion Value Registers 32 7 3-0 33 7-0 Port 7 VLAN Tag Insertion Value Registers ...
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KS8999 Absolute Maximum Ratings Supply Voltage ( DD_RX DD_TX DD_RCV .............................................. –0.5V to +2.3V DD_PLLTX (V ) .................................................... –0.5V to +3.8V DDIO Input Voltage ............................................... –0.5V to +4.0V Output Voltage ...
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KS8999 Symbol Parameter 100BaseTX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion Overshoot V Reference Voltage of ISET SET Output Jitters 10BaseTX Receive V Squelch Threshold SQ 10BaseT Transmit (measured differentially after 1:1 transformer) V Peak Differential Output Voltage ...
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KS8999 Timing Diagrams Symbol Parameter t Clock Cycle CYC t Set-Up Time S t Hold Time H Symbol Parameter t Clock Cycle CYC t Output Valid OV January 2005 Figure 7. EEPROM Input Timing Table 5. EEPROM Input Timing Parameters ...
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KS8999 Symbol Parameter t Clock Cycle CYC t Set-Up Time S t Hold Time H Symbol Parameter t Clock Cycle CYC t Output Valid OV KS8999 Figure 9. SNI (7-wire) Input Timing Table 7. SNI (7-wire) Input Parameters Figure 10. ...
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KS8999 Figure 11. KS8999 PHY Mode—Data Sent from External MAC Controller to KS8999 Symbol Parameter t Clock Cycle (100BaseT) CYC t Clock Cycle (10BaseT) CYC t Set-Up Time S t Hold Time H Table 9. MII Timing in KS8999 PHY ...
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KS8999 Figure 13. KS8999 PHY Mode—Data Sent from KS8999 PHY Mode to External MAC Controller Symbol Parameter t Clock Cycle (100BaseT) CYC t Clock Cycle (10BaseT) CYC t Output Valid OV Table 10. KS8999 PHY Mode Transmit Timing Parameters KS8999 ...
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KS8999 Figure 15. KS8999 MAC Mode—Data Sent from External PHY Device to KS8999 Symbol Parameter t Clock Cycle (100BaseT) CYC t Clock Cycle (10BaseT) CYC t Output Valid S t Output Valid H Table 11. KS8999 PHY Mode Transmit Timing ...
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KS8999 Figure 17. KS8999 MAC Mode Timing—Data Sent from KS8999 MAC mode to External PHY Device Symbol Parameter t Clock Cycle (100BaseT) CYC t Clock Cycle (10BaseT) CYC t Output Valid OV Table 12. KS8999 MAC Mode Transmit Timing Parameters ...
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KS8999 Reference Circuits “I/O Description” See section for pull-up/pull-down and float information. Reset Reference Circuit Micrel recommendeds the following discrete reset circuit as shown in Figure 20 when powering up the KS8999 device. For the application where the reset circuit ...
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KS8999 Figure 21. Recommended Circuit for Interfacing with CPU/FPGA Reset At power-on-reset and D1 provide the necessary ramp rise time to reset the KS8999 device. The reset out from CPU/ FPGA provides warm reset after power up. It ...
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KS8999 4B/5B Coding In 100BaseTX and 100BaseFX the data and frame control are encoded in the transmitter (and decoded in the receiver) using a 4B/5B code. The extra code space is required to encode extra control (frame delineation) points. It ...
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KS8999 MLT3 Coding For 100BaseTX operation the NRZI (Non-Return to Zero Invert on ones) signal is line coded as MLT3. The net result of using MLT3 is to reduce the EMI (Electro Magnetic Interference) of the signal over twisted pair ...
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KS8999 Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name Turns Ratio ...
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KS8999 Package Information MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 TEL The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel ...