KSZ8995M Micrel Inc, KSZ8995M Datasheet - Page 13

• Manufacturer Part Number: KSZ8995M
• Description: IC SWITCH 10/100 5PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8995M

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.9/2.6/3.6V
• Operating Supply Voltage (min): 1.7/2.4/3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1607 - BOARD EVAL EXPERIMENT KSZ8995MA
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1038

Note:
1. P = Power supply
December 2003
KS8995M
Pin Number
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
98
99
SPID/SDA
Pin Name
SPIC/SCL
TESTEN
SPIS_N
LED3-0
LED2-2
LED2-1
LED2-0
LED1-2
LED1-1
LED1-0
RST_N
VDDIO
GNDD
GNDD
VDDC
MDIO
SPIQ
MDC
PS1
PS0
Type
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Gnd
Gnd
Otri
Ipu
I/O
I/O
I/O
Ipu
Ipd
Ipd
Ipu
Ipd
P
P
(1)
Port
All
All
All
All
All
All
3
2
2
2
1
1
1
Pin Function
LED indicator 0
Digital ground
3.3/2.5V digital V
LED indicator 2
LED indicator 1
LED indicator 0
LED indicator 2
LED indicator 1
LED indicator 0
Switch or PHY[5] MII management data clock
Switch or PHY[5] MII management data I/O.
Features internal pull down to define pin state when not driven.
(1) SPI serial data output in SPI slave mode; (2) Not used in I2C master
mode. See “pin# 113.”
(1) Input clock up to 5MHz in SPI slave mode; (2) Output clock at
81KHz in I2C master mode. See “pin# 113.”
(1) Serial data input in SPI slave mode; (2) Serial data input/output in
I2C master mode See “pin# 113.”
Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_N
is high, the KS8995M is deselected and SPIQ is held in high impedance
state, a high-to-low transition to initiate the SPI data transfer; (2) Not
used in I2C master mode.
Serial bus configuration pin
If EEPROM is not present, the KS8995M will start itself with chip
default (00)...
Pin Config.
PS[1:0]=00
PS[1:0]=01
PS[1:0]=10
PS[1:0]=11
Serial bus configuration pin. See “pin# 113.”
Reset the KS8995M. Active low.
Digital ground
1.8V digital core V
NC for normal operation. Factory test pin.
13
DD
DD
for digital I/O
Serial Bus Configuration
I2C Master Mode for EEPROM
Reserved
SPI Slave Mode for CPU Interface
Factory Test Mode (BIST)
M9999-120403
Micrel