IDT89HPES6T5ZBBCG8 IDT, Integrated Device Technology Inc, IDT89HPES6T5ZBBCG8 Datasheet - Page 6

• Manufacturer Part Number: IDT89HPES6T5ZBBCG8
• Description: IC PCI SW 6LANE 5PORT 196-CABGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES6T5ZBBCG8

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 89HPES6T5ZBBCG8

IDT 89HPES6T5 Data Sheet
MSMBSMODE
APWRDISN
GPIO[10]
Signal
Signal
CCLKDS
CCLKUS
PERSTN
GPIO[7]
GPIO[8]
GPIO[9]
Type
Type
I/O
I/O
I/O
I/O
I
I
I
I
I
Table 4 General Purpose I/O Pins (Part 2 of 2)
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P3RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 3
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P5RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 5
Auxiliary Power Disable Input. When this pin is active, it disables the
device from using auxiliary power supply.
Common Clock Downstream. The assertion of this pin indicates that all
downstream ports are using the same clock source as that provided to
downstream devices.This bit is used as the initial value of the Slot Clock
Configuration bit in all of the Link Status Registers for downstream ports.
The value may be override by modifying the SCLK bit in the downstream
port’s PCIELSTS register.
Common Clock Upstream. The assertion of this pin indicates that the
upstream port is using the same clock source as the upstream device. This
bit is used as the initial value of the Slot Clock Configuration bit in the Link
Status Register for the upstream port. The value may be overridden by
modifying the SCLK bit in the PA_PCIELSTS register.
Master SMBus Slow Mode. The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 kHz. This value
may not be overridden.
Fundamental Reset. Assertion of this signal resets all logic inside the
PES6T5 and initiates a PCI Express fundamental reset.
Table 5 System Pins (Part 1 of 2)
6 of 28
Name/Description
Name/Description
May 7, 2009