IDT89HPES12N3AZGBC IDT, Integrated Device Technology Inc, IDT89HPES12N3AZGBC Datasheet - Page 3

• Manufacturer Part Number: IDT89HPES12N3AZGBC
• Description: IC PCI SW 12LANE 3PORT 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES12N3AZGBC

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES12N3AZGBC

Hot-Plug Interface
utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura-
tion, whenever the state of a Hot-Plug output needs to be modified, the PES12N3A generates an SMBus transaction to the I/O expander with the new
value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin
(alternate function of GPIO) of the PES12N3A. In response to an I/O expander interrupt, the PES12N3A generates an SMBus transaction to read the
state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
pin may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
action layers in compliance with PCI Express Base specification Revision 1.1. The PES12N3A can operate either as a store and forward or cut-
through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with
sophisticated resource management to enable efficient switching and I/O connectivity for servers, storage, and embedded applications.
IDT 89HPES12N3A Data Sheet
The PES12N3A supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES12N3A
The PES12N3A provides eight General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO
The PES12N3A is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Trans-
PES12N3A
(a) Unified Configuration and Management Bus
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
Processor
SMBus
Master
EEPROM
Figure 2 SMBus Interface Configuration Examples
PCI Express
Serial
PES12N3A
Slots
Figure 3 I/O Expansion Application
...
Devices
SMBus
Other
Dual
GbE
I/O
PES12N3A
Processor
3 of 31
Bridge
North
Dual
GbE
I/O
SATA
I/O
(b) Split Configuration and Management Buses
Memory
Memory
PES12N3A
Memory
Memory
PES12N3A
SATA
I/O
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
Processor
SMBus
Master
EEPROM
Serial
...
Devices
SMBus
Other
April 9, 2010