IDT89HPES16T7ZHBX IDT, Integrated Device Technology Inc, IDT89HPES16T7ZHBX Datasheet - Page 4

• Manufacturer Part Number: IDT89HPES16T7ZHBX
• Description: IC PCI SW 16LANE 7PORT 320-SBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES16T7ZHBX

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES16T7ZHBX

Hot-Plug Interface
utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura-
tion, whenever the state of a Hot-Plug output needs to be modified, the PES16T7 generates an SMBus transaction to the I/O expander with the new
value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin
(alternate function of GPIO) of the PES16T7. In response to an I/O expander interrupt, the PES16T7 generates an SMBus transaction to read the
state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
IDT 89HPES16T7 Data Sheet
The PES16T7 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES16T7
The PES16T7 provides 12 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin
The following tables lists the functions of the pins provided on the PES16T7. Some of the functions listed may be multiplexed onto the same pin.
PE0RN[3:0]
PE1RN[3:0]
PE6RN[3:0]
PE0RP[3:0]
PE0TP[3:0]
PE0TN[3:0]
PE1RP[3:0]
PE1TP[3:0]
PE1TN[3:0]
PE6RP[3:0]
PE2RP[0]
PE2RN[0]
PE2TN[0]
PE3RP[0]
PE3RN[0]
PE3TN[0]
PE4RP[0]
PE4RN[0]
PE4TN[0]
PE5RP[0]
PE5RN[0]
PE5TN[0]
PE2TP[0]
PE3TP[0]
PE4TP[0]
PE5TP[0]
Signal
Type
O
O
O
O
O
O
I
I
I
I
I
I
I
Table 2 PCI Express Interface Pins (Part 1 of 2)
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0.
PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0.
PCI Express Port 1 Serial Data Receive. Differential PCI Express receive
pairs for port 1.
PCI Express Port 1 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 1.
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pair for port 3.
PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 3.
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pair for port 4.
PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 4.
PCI Express Port 5 Serial Data Receive. Differential PCI Express receive
pair for port 5.
PCI Express Port 5 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 5.
PCI Express Port 6 Serial Data Receive. Differential PCI Express receive
pair for port 6.
4 of 33
Name/Description
March 25, 2008