IDT89HPES16T4G2ZABX IDT, Integrated Device Technology Inc, IDT89HPES16T4G2ZABX Datasheet - Page 11
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IDT89HPES16T4G2ZABX
Manufacturer Part Number
IDT89HPES16T4G2ZABX
Description
IC PCI SW 16LANE 4PORT 288-SBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT89HPES16T4G2ZABX8.pdf
(31 pages)
Specifications of IDT89HPES16T4G2ZABX
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
89HPES16T4G2ZABX
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT89HPES16T4G2ZABX
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT89HPES16T4G2ZABX8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT89HPES16T4G2ZABXG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT89HPES16T4G2ZABXG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
System Clock Parameters
AC Timing Characteristics
IDT 89HPES16T4G2 Data Sheet
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 15.
Refclk
T
T
V
V
V
V
V
T
T
T
T
V
V
Duty Cycle
Rise/Fall Matching
Z
1.
C-RISE
C-FALL
IH
IL
CROSS
CROSS-DELTA
RB
STABLE
PERIOD-AVG
PERIOD-ABS
CC-JITTER
MAX
MIN
C-DC
PCIe Transmit
UI
T
T
MAX-JITTER
T
T
Parameter
The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM.
TX-EYE
TX-EYE-MEDIAN-to-
TX-RISE
TX- IDLE-MIN
Parameter
FREQ
, T
TX-FALL
Input reference clock frequency range
Rising edge rate
Falling edge rate
Differential input high voltage
Differential input low voltage
Absolute single-ended crossing point
voltage
Variation of V
edges
Ring back voltage margin
Time before V
Average clock period accuracy
Absolute period, including spread-spec-
trum and jitter
Cycle to cycle jitter
Absolute maximum input voltage
Absolute minimum input voltage
Duty cycle
Single ended rising Refclk edge rate ver-
sus falling Refclk edge rate
Clock source output DC impedance
Unit Interval
Minimum Tx Eye Width
Maximum time between the jitter median and maximum
deviation from the median
TX Rise/Fall Time: 20% - 80%
Minimum time in idle
Description
CROSS
RB
is allowed
Description
over all rising clock
Table 10 PCIe AC Timing Characteristics (Part 1 of 2)
Table 9 Input Clock Requirements
Condition
Single-ended
Single-ended
11 of 31
Differential
Differential
Differential
Differential
Differential
Differential
Min
399.88
0.125
0.75
20
1
Gen 1
Typ
400
9.847
Min
+150
+250
-100
-300
1
100
500
-0.3
0.6
0.6
40
40
Max
400.12
0.125
1
Typical
Min
199.94
0.75
0.15
20
20
1
Gen 2
Typ
200
1
10.203
Max
+1.15
+550
+140
+100
2800
125
-150
150
60
60
4
4
Max
September 13, 2010
200.06
1
1
Units
Unit
MHz
V/ns
V/ns
ps
ppm
UI
UI
UI
UI
mV
mV
mV
mV
mV
ps
ns
ps
%
%
Ω
V
V