IDT77V400S156BCG IDT, Integrated Device Technology Inc, IDT77V400S156BCG Datasheet - Page 16

• Manufacturer Part Number: IDT77V400S156BCG
• Description: IC SW MEMORY 8X8 1.2BGPS 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V400S156BCG

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 77V400S156BCG

bus mode and a cell is not ready for dispatch. Upon receiving a HIGH OFRMx input, the Switching Memory will hold if a transmission was beginning.
When an output port asserts OFRMx HIGH all of Switching Memories on the bus, including the transmitting Switching Memory, reset the internal start
of frame count. The transmitting IDT77V400 then places the data on the output bus and all Switching Memories on the bus count to the end of the
frame. If OFRMx is an output, the internal OSAMx counter is set to the starting address. The counter will count up to the stop address for each subse-
quent OCLKx rising edge after OFRMx goes low. In this manner, all devices sharing the output bus must be set to the same nibble count. if a switching
memory receives a ldx command while any port is transmitting on the output bus, it will continue counting and wait for the stop address to be reached
before asserting ofrmx and dispatching a cell. this will avoid collisions on the bus; however, it is the responsibility of the external controller to issue only
one ldx command for a shared cell bus within a single cell transmit time.
Functional Waveforms
Functional Waveforms
Functional Waveforms
Functional Waveforms
1
2
the command used.
3
4
1
2
command used.
3
4
IDT77V400
The Memory Store Cycle requires four cycles to write the cell from the ISAM to the Buffer Memory.
The PPE or PHEC commands can be executed at this point in the sequence instead of the PHE command. The IOD bus would then reflect the appropriate bytes in the cell based on
The 13-bit cell address, 4-bit selected Switching Memory address, and 5-bit Edit Buffer Protect and Clear control bits are valid at this time.
STORE ISAM command can only be valid for one cycle during a Memory Store Cycle. Issuing more than one STORE ISAM will cause Buffer Memory write failure.
The Memory Load Cycle requires four cycles to write the cell from the Buffer Memory to the OSAM.
The OPE or OHEC commands can be executed at this point in the sequence instead of the OHE command. The IOD bus would then reflect the appropriate cell bytes based on the
The 13-bit cell address and 4-bit selected Switching Memory address are valid at this time
LOAD OSAM command can only be valid for one cycle during a Load Sequence. Issuing more than one LOAD OSAM will cause Buffer Memory read failure.
The OFRM pin is always monitored internally by the Switching Memory. The OFRMx output is released to a High-impedance state when it is in cell
IOD BUS
CMD0-5
CMD0-5
IOD BUS
IOD0-31
IOD0-31
MODE
MODE
SCLK
SCLK
CS
CS
Input
Input
GET HEADER
HEADER
GET
ISAM
Output
Output
Header
Header
Old
Old
STORE
OSAM
LOAD
ISAM
4
4
Figure 6 Functional Waveform - Store Instruction Sequence
Figure 7 Functional Waveform - Load Instruction Sequence
Input
Input
Address
Address
Cell
Cell
HEADER
HEADER
PUT
3
OR
3
2
2
Input
Input
Header
Header
Data
New
16 of 26
STATUS
2
2
STATUS
GET
GET
MEMORY STORE SEQUENCE
Output
Output
LOAD SEQUENCE
Status
Status
Port
Port
MEMORY STORE CYCLE
Input
Input
LOAD CYCLE
1
Input
Input
1
March 31, 2001
Input
Input
3606 drw 12
3606 drw 13