IDT72V51546L6BB8 IDT, Integrated Device Technology Inc, IDT72V51546L6BB8 Datasheet - Page 12

• Manufacturer Part Number: IDT72V51546L6BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51546L6BB8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51546L6BB8

PIN DESCRIPTIONS (CONTINUED)
NOTES:
1. Inputs should not change after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 53-57 and Figures 33-35.
PIN NUMBER TABLE
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
WCLK
(Continued)
(T7)
WEN
(T6)
WRADD
[7:0]
(WRADD7-T1
WRADD6-R1
WRADD5-R2
WRADD4-P1
WRADD3-P2
WRADD2-P3
WRADD1-N1
WRADD0-N2)
V
(See below)
GND
(See below)
D[35:0]
Din
PAEn/PRn Programmable Almost-
PAFn
Q[35:0]
Qout
V
GND
DNC
Symbol
CC
CC
Symbol &
Pin No.
Data Input Bus
Empty Flag Bus/Packet
Ready Flag Bus
Programmable Almost-
Full Flag Bus
Data Output Bus
+3.3V Supply
Ground Pin
Do Not Connect
Write Clock
Write Enable
Write Address Bus
+3.3V Supply
Ground Pin
Name
Name
I/O TYPE
Ground
I/O TYPE
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
OUTPUT
OUTPUT
OUTPUT Q(21,20)-D(15,16), Q19-B16, Q(18,17)-C(16,15), Q16-D14, Q(15,14)-A(16,15), Q13-B15, Q12-A14,
Power
Ground
LVTTL
INPUT
LVTTL
LVTTL
LVTTL
Power
bus is cycled with respect to WCLK and the FSYNC signal is synchronized to WCLK. The PAFn, PAF and
FF outputs are all synchronized to WCLK. During device expansion the FXO and FXI signals are based
on WCLK. The WCLK must be continuous and free-running.
The WEN input enables write operations to a selected queue based on a rising edge of WCLK. A queue
to be written to can be selected via WCLK, WADEN and the WRADD address bus regardless of the state
of WEN. Data present on Din can be written to a newly selected queue on the second WCLK cycle after
queue selection provided that WEN is LOW. A write enable is not required to cycle the PAFn bus (in polled
mode) or to select the PAFn quadrant , (in direct mode).
For the 32Q device the WRADD bus is 8 bits. The WRADD bus is a dual purpose address bus. The
first function of WRADD is to select a queue to be written to. The least significant 5 bits of the bus, WRADD[4:0]
are used to address 1 of 32 possible queues within a multi-queue device. The most significant 3 bits,
mode. These 3 MSB’s will address a device with the matching ID code. The address present on the
WRADD bus will be selected on a rising edge of WCLK provided that WADEN is HIGH, (note, that data
present on the Din bus can be written into the previously selected queue on this WCLK edge and on the
next rising WCLK also, providing that WEN is LOW). Two WCLK rising edges after write queue select,
data can be written into the newly selected queue.
The second function of the WRADD bus is to select the quadrant of queues to be loaded on to the PAFn
bus during strobed flag mode. The least significant 2 bits, WRADD[1:0] are used to select the quadrant
of a device to be placed on the PAFn bus. The most significant 3 bits, WRADD[7:5] are again used to select
1 of 8 possible multi-queue devices that may be connected in expansion mode. Address bits WRADD[4:2]
are don’t care during quadrant selection. The quadrant address present on the WRADD bus will be selected
on the rising edge of WCLK provided that FSTR is HIGH, (note, that data can be written into the previously
selected queue on this WCLK edge). Please refer to Table 1 for details on the WRADD bus.
These are V
These are Ground pins and must all be connected to the GND supply rail.
WRADD[7:5] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion
D35-J3, D(34-32)-H(3-1), D(31-29)-G(3-1), D(28-26)-F(3-1), D(25-23)-E(3-1), D(22-20)-D(3-1),
D(19-17)-C(3-1), D(16,15)-B(2,1), D(14-12)-A(1-3), D11-B3, D10-A4, D9-B4, D8-C4, D7-A5,
D6-B5, D5-C5, D4-A6, D3-B6, D2-C6, D1-A7, D0-B7
PAE7-P11, PAE6-P12, PAE5-R12, PAE4-T12, PAE3-P13, PAE2-R13, PAE1-T13, PAE0-T14
PAF7-P7, PAF6-P6, PAF5-R6, PAF4-R7, PAF3-P5, PAF2-R5, PAF1-T5, PAF0-T4
Q(35,34)-J(15,16), Q(33-31)-H(14-16), Q(30-28)-G(14-16), Q(27-25)-F(14-16), Q(24-22)-E(14-16),
Q11-B14, Q10-C14, Q9-A13, Q8-B13, Q7-C13, Q6-A12, Q5-B12, Q4-C12, Q3-A11, Q2-B11,
Q(1,0)-C(11,10)
D(4-13), E(4-7,10-13), F(4,5,12,13), G(4,5,12,13), H(4,13), J(4,13), K(4,5,12,13), L(4,5,12,13),
M(4-7,10-13), N(4-13)
C8, E(8-9), F(6-11), G(6-11), H(5-12), J(1,2,5-12), K(1-3,14,6-11), L(6-11), M(8-9)
R(10,11)
CC
power supply pins and must all be connected to a +3.3V supply rail.
12
Description
Pin Number
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES