IDT72T55248L6-7BBI IDT, Integrated Device Technology Inc, IDT72T55248L6-7BBI Datasheet - Page 3

• Manufacturer Part Number: IDT72T55248L6-7BBI
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55248L6-7BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55248L6-7BBI

Figure 1. QuadMux Block Diagram .................................................................................................................................................................................. 7
Figure 2a. AC Test Load ................................................................................................................................................................................................ 18
Figure 2b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 18
Figure 3. Programmable Flag Offset Programming Methods ........................................................................................................................................... 21
Figure 4. Offset Registers Serial Bit Sequence ................................................................................................................................................................ 22
Figure 5. Bus-Matching Byte Arrangement (Mux, DeMux and Broadcast Mode) ....................................................................................................... 25-27
Figure 6. Echo Read Clock and Data Output Relationship .............................................................................................................................................. 35
Figure 7. Standard JTAG Timing ................................................................................................................................................................................... 36
Figure 8. JTAG Architecture ........................................................................................................................................................................................... 37
Figure 9. TAP Controller State Diagram ......................................................................................................................................................................... 38
Figure 10. Master Reset ................................................................................................................................................................................................ 41
Figure 11. Partial Reset for Mux mode ........................................................................................................................................................................... 42
Figure 12. Partial Reset for Demux mode ...................................................................................................................................................................... 43
Figure 13. Partial Reset for Broadcast mode .................................................................................................................................................................. 44
Figure 14. Write Cycle and Full Flag Timing (Mux mode, IDT Standard mode, SDR to SDR) x10 In to x40 Out ............................................................. 45
Figure 15. Write Cycle and Full Flag Timing (Broadcast Write mode, IDT Standard mode, SDR to SDR) x10 In to x10 Out ............................................ 46
Figure 16. Write Cycle and Full Flag Timing (Demux mode, IDT Standard mode, SDR to SDR) x10 In to x10 Out ......................................................... 47
Figure 17. Write Timing (Mux mode, FWFT mode, SDR to SDR) x10 In to x10 Out ........................................................................................................ 48
Figure 18. Write Timing (Broadcast Write mode, FWFT mode, SDR to SDR) x10 In to x10 Out ....................................................................................... 49
Figure 19. Write Timing (Demux mode, FWFT mode, SDR to SDR) x10 In to x10 Out ................................................................................................... 50
Figure 20. Read Cycle, Empty Flag and First Word Latency (Mux mode, IDT Standard mode, SDR to SDR) x10 In to x40 Out ..................................... 51
Figure 21. Read Timing (Broadcast Write mode, FWFT mode, SDR to SDR) x10 In to x10 Out ...................................................................................... 52
Figure 22. Read Timing (Mux mode, FWFT mode, SDR to SDR) x10 In to x10 Out ....................................................................................................... 53
Figure 23. Read Timing (Demux mode, FWFT mode, SDR to SDR) x20 In to x10 Out .................................................................................................. 53
Figure 24. Read Cycle, Empty Flag and First Word Latency (Demux mode, IDT Standard mode, SDR to SDR) x20 In to x10 Out ................................. 54
Figure 25. Read Cycle, Empty Flag and First Word Latency (Broadcast Write mode, IDT Standard mode, SDR to SDR) x40 In to x10 Out .................... 55
Figure 26. Composite Empty Flag (Mux mode, IDT Standard mode, SDR to SDR) x10 In to x40 Out ............................................................................. 56
Figure 27. Composite Output Ready Flag (Mux mode, FWFT mode, SDR to SDR) x10 In to x40 Out ............................................................................ 56
Figure 28. Composite Full Flag (Demux mode, IDT Standard mode, SDR to SDR) x20 In to x10 Out ............................................................................ 57
Figure 29. Composite Input Ready Flag (Demux mode, FWFT mode, SDR to SDR) x20 In to x10 Out .......................................................................... 57
Figure 30. Echo Read Clock and Read Enable Operation (Mux/Demux/Broadcast mode, IDT Standard mode, DDR to DDR) x10 In to x10 Out ........... 58
Figure 31. Echo RCLK and Echo Read Enable Operation (Mux/Demux/Broadcast mode, FWFT mode, SDR to SDR) .................................................. 59
Figure 32. Echo Read Clock and Read Enable Operation (Mux/Demux/Broadcast mode, IDT Standard mode, SDR to SDR) x10 In to x10 Out ........... 60
Figure 33. Loading of Programmable Flag Registers (IDT Standard and FWFT modes) ................................................................................................ 61
Figure 34. Reading of Programmable Flag Registers (IDT Standard and FWFT modes) ................................................................................................ 61
Figure 35. Synchronous Programmable Almost-Full Flag Timing (see page for details) ................................................................................................... 62
Figure 36. Synchronous Programmable Almost-Empty Flag Timing (see page for details) ............................................................................................... 62
Figure 37. Asynchronous Programmable Almost-Full Flag Timing (see page for details) ................................................................................................ 63
Figure 38. Asynchronous Programmable Almost-Empty Flag Timing (see page for details) ............................................................................................ 63
Figure 39. Power Down Operation ................................................................................................................................................................................ 64
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
List of Figures
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 01, 2009