IDT72T55268L6-7BB IDT, Integrated Device Technology Inc, IDT72T55268L6-7BB Datasheet - Page 20

• Manufacturer Part Number: IDT72T55268L6-7BB
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55268L6-7BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55268L6-7BB

FUNCTIONAL DESCRIPTION
MASTER RESET & DEVICE CONFIGURATION - MRS
following:
of the above modes are selected. A Master Reset comprises of pulsing the MRS
input ping from high to low for a period of time (t
held in their respective states. Table 1 summarizes the configuration modes
available doing master reset. The are described as follows:
TABLE 1 — DEVICE CONFIGURATION
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
FSEL[1:0]
During Master Reset the device operation is determined, this includes the
1. Mux, Demux or Broadcast mode
2. IDT Standard or First Word Fall Through (FWFT) flag timing mode
3. Single or Double Data Rates on both the Write and Read ports
4. Programmable flag mode, synchronous or asynchronous timing
5. Write and read port bus widths, x10, x20 or x40
6. Default offsets for the programmable flags, 7, 63, 127 or 1023
7. LVTTL or HSTL I/O level selection
8. Input and output Queue selection
The state of the configuration inputs during a master reset will determine which
FWFT/SI
MD[1:0]
OW[1:0]
OS[1:0]
WDDR
IW[1:0]
IOSEL
RDDR
IS[1:0]
PINS
PFM
VALUES
00
10
01
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
0
1
0
1
0
1
0
1
0
1
Demux
Mux
Broadcast Write
Restricted
IDT Standard
FWFT
Single Data Rate write port
Double Data Rate write port
Single Data Rate read port
Double Data Rate read port
Asynchronous operation of PAE and PAF outputs
Synchronous operation of PAE and PAF outputs
Write port is 10 bits wide
Write port is 20 bits wide
Write port is 40 bits wide
Restricted
Read port is 10 bits wide
Read port is 20 bits wide
Read port is 40 bits wide
Restricted
Programmable flag offset registers value = 7
Programmable flag offset registers value = 63
Programmable flag offset registers value = 127
Programmable flag offset registers value = 1023
All applicable I/Os (except CMOS) are LVTTL
All applicable I/Os (except CMOS) are HSTL/eHSTL
Mux/Broadcast Mode
Mux Mode
not used
not used
not used
not used
Queue0
Queue1
Queue2
Queue3
CONFIGURATION
RS
) with the configuration inputs
Demux/Broadcast Mode
Demux Mode
not used
not used
not used
not used
Queue0
Queue1
Queue2
Queue3
20
If during master reset, MD1 is HIGH and MD0 is LOW then Mux mode is selected.
If MD1 and MD2 are LOW then Demux is selected. If MD1 is LOW and MD0
is HIGH then Broadcast mode is selected.
selected using the FWFT/SI input. If FWFT/SI is LOW during Master Reset then
IDT Standard mode is selected, if it is high then FWFT mode is selected.
data rates are port selectable. This is a versatile feature that allows the user to
select either SDR or DDR on the write port(s) and/or read(s) port using the
WDDR and/or RDDR inputs. If WDDR is LOW during master reset then the write
port(s) will function in SDR mode, if it is high then the write port will be DDR mode.
If RDDR is LOW during master reset then the read port(s) will function in SDR
mode, if it is high then the read port will be DDR mode. Note that WDDR will select
the data rate mode for the single write port in Demux and Broadcast mode and
all four write ports in Mux mode. Likewise, RDDR will select the data rate mode
for the single read port in Mux mode and all four read ports in Demux and
Broadcast mode.
either synchronous or asynchronous timing mode. If the programmable flag
input, PFM is HIGH during master reset then all programmable flags will operate
in a synchronous manner, meaning the PAE flags are double buffered and
updated based on the rising edge of its respective read clocks. The PAF flags
are also double buffered and updated based on the rising edge of its respective
write clocks. If it is LOW then all programmable flags will operate in an
asynchronous manner, meaning the PAE and PAF flags are not double buffered
and will update through the internal counter after a nominal delay.
Demux and Broadcast mode and on the read port in Mux mode. In Demux and
Broadcast mode the write port width is selected using the IW[1:0] inputs. If IW0
and IW1 are LOW then the write port will be 10 bits wide, if IW0 is LOW and IW1
is HIGH then the write port will be 20 bits wide, if IW0 is HIGH and IW1 is LOW
then the write port will be 40 bits wide. Note, in Demux and Broadcast mode all
read ports are 10 bits wide. In Mux mode the read port width is selected using
the OW[1:0] inputs. If OW0 and 0W1 are LOW then the read port will be 10 bits
wide, if OW0 is LOW and OW1 are HIGH then the read port will be 20 bits wide,
if OW0 is HIGH and OW1 are LOW then the read port will be 40 bits wide. Note,
in Mux mode all write ports are 10 bits wide.
programmed or they can be set to one of four default values during a master
reset. For default programming, the state of the FSEL[1:0] inputs during master
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. In default programming, the offset value selected applies to all internal Queues.
2. To program different offset values for each Queue, serial programming must be used.
Mux/Demux/Broadcast. This mode is selected using the MD[1:0] inputs.
IDT Standard or FWFT Mode. The two available flag timing modes are
Single Data Rate (SDR) or Double Data Rate (DDR). The input/output
Programmable Almost Empty/Full Flags. These flags can operate in
Selectable Bus Width. The bus width can be selected on the write port in
Programmable Flag Offset Values. These offset values can be user
FSEL1
0
0
1
1
IDT72T55248
IDT72T55258
IDT72T55268
FSEL0
0
1
0
1
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 01, 2009
Offsets n,m
1,023
127
63
7