IDT72P51777L7-5BBI IDT, Integrated Device Technology Inc, IDT72P51777L7-5BBI Datasheet - Page 11

• Manufacturer Part Number: IDT72P51777L7-5BBI
• Description: IC FLOW CTRL 40BIT 376-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51777L7-5BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51777L7-5BBI

PIN DESCRIPTIONS (CONTINUED)
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
FF (Continued) Full Flag
(E1)
FM
(U2)
FSTR
(T2)
FSYNC
(J2)
FXI
(T1)
FXO
(J3)
ID[2:0]
(ID2-A12
ID1-B12
ID0-A13)
MAST
(U1)
MRS
(T3)
Symbol &
Pin No.
Flag Mode
PAFn Flag
Bus Strobe
PAFn Bus Sync
PAFn Bus
Expansion In
PAFn Bus
Expansion Out
Device ID Pins
Master Device
Master Reset
Name
1.8V LVTTL
1.8V LVTTL
1.8V LVTTL
I/O TYPE
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
This pin is setup before a Master Reset and must not toggle during any device operation. The state of the
devices, when the FF flag output of up to 8 devices may be connected together on a common line. The
device with a queue selected takes control of the FF bus, all other devices place their FF output into High-
Impedance. When a queue selection is made on the write port this output will switch from High-Impedance
control on the next WCLK cycle. This flag is asserted synchronous to WCLK.
FM pin during Master Reset will determine whether the PAFn and PAEn flag busses operate in either Polled
or Direct mode. If FM is HIGH, Polled mode is selected, if FM LOW, Direct mode is selected.
If direct mode for the PAFn bus has been selected, the FSTR input is used in conjunction with WCLK and
the WRADD bus to select a quadrant of queues to be placed on to the PAFn bus outputs. A quadrant
addressed via the WRADD bus is selected on the rising edge of WCLK provided that FSTR is HIGH. If
polled operations has been selected, FSTR should be tied inactive, LOW. Note, that a PAFn flag bus
selection cannot be made, (FSTR must NOT go active) until programming of the part has been completed
and SENO has gone LOW.
FSYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAFn bus
during Polled operation of the PAFn bus. During Polled operation each quadrant of queue status flags
is loaded on to the PAFn bus outputs sequentially based on WCLK. The first WCLK rising edge loads
quadrant 1 on to PAFn, the second WCLK rising edge loads quadrant 2 and so on. The fifth WCLK rising
edge will again load quadrant 1 queue status flags. During the WCLK cycle that quadrant 1 of a selected
device is placed on to the PAFn bus, the FSYNC output will be HIGH. For all other quadrants of that device,
the FSYNC output will be LOW.
The FXI input is used when multi-queue devices are connected in expansion mode and Polled PAFn bus
operation has been selected . FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI receives
a token from the previous device in a chain. In single device mode the FXI input must be tied LOW if the
PAFn bus is operated in direct mode. If the PAFn bus is operated in polled mode the FXI input must be
connected to the FXO output of the same device. In expansion mode the FXI of the first device should be
tied LOW, when direct mode is selected.
FXO is an output that is used when multi-queue devices are connected in expansion mode and Polled
PAFn bus operation has been selected . FXO of device ‘N’ connects directly to FXI of device ‘N+1’. This
pin pulses when device N has placed its final (4th) quadrant on to the PAFn bus with respect to WCLK.
This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next WCLK rising
edge the first quadrant of device N+1 will be loaded on to the PAFn bus. This continues through the chain
and FXO of the last device is then looped back to FXI of the first device. The FSYNC output of each device
in the chain provides synchronization to the user of this looping event.
The ID[2:0] pins are used to uniquely address individual devices when multiple Multi-Queue devices are
connected in expansion mode. Addressing devices in expansion mode requires matching WRADD/
RDADD address bits with the address that is assigned to each device by the ID[2:0] pins. During write/
read operations the WRADD/RDADD address are compared to the device ID [2:0] value. Note:
expansion mode supports a maximum 256 queues, regardless of the number of devices used in expansion
mode. The first device in a chain of multi-queue’s (connected in expansion mode), may be setup as ‘000’,
the second as ‘001". In single device mode the ID[2:0] pins should be setup as ‘0xx’ and the MSb (bit
7) of the WRADD and RDADD address busses should be zero. The ID[2:0] inputs setup a respective
device ID during Master Reset. These ID pins must not toggle during any device operation. Note, the device
selected as the ‘Master’ does not have to have the ID of ‘000’.
The state of this input at Master Reset determines whether a given device (within a chain of devices), is
the Master device or a Slave. If this pin is HIGH, the device is the master if it is LOW then it is a Slave. The
master device is the first to take control of all outputs after a Master Reset, all slave devices go to High-
Impedance, preventing bus contention. If a multi-queue device is being used in single device mode, this
pin must be set HIGH.
The Master Reset is used to configure the device. To configure the device configuration signals must be
asserted that meet the setup time and hold time requirements of a Master Reset cycle. Transitioning MRS
from HIGH to LOW then LOW to HIGH performs a complete Master Reset cycle. Note, additional device
programming is required after master reset.
11
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009