DS28CM00R-A00+T Maxim Integrated Products, DS28CM00R-A00+T Datasheet - Page 6

• Manufacturer Part Number: DS28CM00R-A00+T
• Description: IC SILICON SERIAL NUMBER SOT23-5
• Manufacturer: Maxim Integrated Products

Specifications of DS28CM00R-A00+T

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: SOT-23-5, SC-74A, SOT-25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 4. I²C/SMBus Protocol Overview
Bus Idle or Not Busy
Both, SDA and SCL, are inactive, i. e., in their logic HIGH states.
START Condition
To initiate communication with a slave, the master has to generate a START condition. A START condition is
defined as a change in state of SDA from HIGH to LOW while SCL remains HIGH.
STOP Condition
To end communication with a slave, the master has to generate a STOP condition. A STOP condition is defined as
a change in state of SDA from LOW to HIGH while SCL remains HIGH.
Repeated START Condition
Repeated starts are commonly used for read accesses to select a specific data source or address to read from.
The master can use a repeated START condition at the end of a data transfer to immediately initiate a new data
transfer following the current one. A repeated START condition is generated the same way as a normal START
condition, but without leaving the bus idle after a STOP condition.
Data Valid
With the exception of the START and STOP condition, transitions of SDA may occur only during the LOW state of
SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the required
setup and hold time (t
There is one clock pulse per bit of data. Data is shifted into the receiving device during the rising edge of the SCL
pulse.
When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum
t
SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL
pulse. The master generates all SCL clock pulses, including those needed to read from a slave.
Acknowledged
Usually, a receiving device, when addressed, is obliged to generate an acknowledge after the receipt of each byte.
The master must generate a clock pulse that is associated with this acknowledge bit. A device that acknowledges
must pull SDA LOW during the acknowledge clock pulse in such a way that SDA is stable LOW during the HIGH
period of the acknowledge-related clock pulse plus the required setup and hold time (t
SCL and t
SU:DAT
SDA
SCL
+ t
Idle
R
SU:DAT
in Figure 5) before the next rising edge of SCL to start reading. The slave shifts out each data bit on
Condition
START
before the rising edge of SCL).
HD:DAT
MS-bit
1
after the falling edge of SCL and t
Slave Address
2
6
7
R/ W
Acknowledgment
8
from Receiver
6 of 9
ACK
ACK
bit
9
SU:DAT
1
DS28CM00: I²C/SMBus Silicon Serial Number
before the rising edge of SCL, see Figure 5).
Repeated if more bytes
2
are transferred
8
ACK
HD:DAT
ACK
bit
9
after the falling edge of
STOP Condition
Repeated START
Condition