CS8190EDWFR20G ON Semiconductor, CS8190EDWFR20G Datasheet - Page 7

• Manufacturer Part Number: CS8190EDWFR20G
• Description: IC DRVR AIRCORE TACH/SPD 20SOIC
• Manufacturer: ON Semiconductor
• Type: Driverr

Specifications of CS8190EDWFR20G

• Applications: Automotive
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Operating Supply Voltage: 13.1 V
• Supply Current: 125 mA
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: CS8190EDWFR20GOS; CS8190EDWFR20GOS; CS8190EDWFR20GOSTR

flutter especially at low input frequencies.
constant formed by RT and C4. Increasing the value of C4
will reduce the ripple on the F/V output but will also increase
the response time. An increase in response time causes a
very slow meter movement and may be unacceptable for
many applications.
the input comparator when V
With no input signal the F/V output voltage decreases and the
needle moves towards zero. A second undervoltage detect
circuit at 6.0 V(typical) causes the function generator to
Ripple voltage on the F/V output causes pointer or needle
The response time of the F/V is determined by the time
The CS8190 has an undervoltage detect circuit that disables
FREQ
FREQ
SQ
V
I
CP+
OUT
CP+
IN
IN
0
0
0
CC
2.0 V
+
−
Figure 7. Partial Schematic of Input and Charge Pump
falls below 8.0 V(typical).
SQ
V
V
OUT
REG
CC
R3
Figure 8. Timing Diagram of FREQ
V
REG
Q
SQUARE
+
V
t
C
DCHG
C
CP
(t)
−
http://onsemi.com
R4
CS8190
7
T
CP+
generate a differential SIN drive voltage of zero volts and the
differential COS drive voltage to go as high as possible. This
combination of voltages (Figure 2) across the meter coil
moves the needle to the 0° position. Connecting a large
capacitor(> 2000 mF) to the V
increases the time between these undervoltage points since
the capacitor discharges slowly and ensures that the needle
moves towards 0° as opposed to 360°. The exact value of the
capacitor depends on the response time of the system,the
maximum meter deflection and the current consumption of
the circuit. It should be selected by breadboarding the design
in the lab.
0.25 V
Q1
t
CHG
IN
Q3
and I
Q2
CP
CP−
2.0 V
CC
+
−
lead (C2 in Figure 9)
C4
R
T
F/V
OUT
F to V