KS8993FL Micrel Inc, KS8993FL Datasheet
KS8993FL
Specifications of KS8993FL
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KS8993FL Summary of contents
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... Block Diagram Micrel is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 ( June 2009 The KS8993FL is the identical rich features of the KS8993F. Features • First single-chip 10BASE-T/100BASE-TX to 100BASE-FX media converter with TS-1000 OAM • ...
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... CMOS technology • Voltages: Core 1.8V I/O and Transceiver 3.3V • Available in 128-pin PQFP Ordering Information Part Number Temperature Pb-Free Standard KSZ8993F KS8993F KSZ8993FL KS8993FL 2 hbwhelp@micrel.com KS8993F/FL Package Range – 128- PQFP – 128- PQFP ...
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... Updated pin description for pin 22 to the following: VDDC : For KS8993F, this is an input power pin for the 1.8V digital core VDD. VOUT_1V8 : For KS8993FL, this is an 1.8V output power pin to supply the KS8993FL’s input power pins: VDDAP (pin 63), VDDC (pins 91, 123) and VDDA (pins 38, 43, 57) ...
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Micrel, Inc. Table Of Contents 1 Signal Description.........................................................................................................................9 1.1 KS8993F Pin Diagram ........................................................................................................................................................... 9 1.2 Pin Description and I/O Assignment .................................................................................................................................... 10 2 Functional Description ................................................................................................................20 2.1 Overview .............................................................................................................................................................................. 20 2.2 Media Converter Function.................................................................................................................................................... 20 2.2.1 OAM (Operations, Administration, and ...
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Micrel, Inc. Register 5: Auto-Negotiation Link Partner Ability ................................................................................................................ 49 4 Register Map: Switch, MC, & PHY (8 bits registers) ..................................................................50 4.1 Global Registers................................................................................................................................................................... 51 Register 0 (0x00): Chip ID0................................................................................................................................................. 51 Register 1 (0x01): Chip ID1 / Start Switch........................................................................................................................... 51 ...
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Micrel, Inc. Register 88 (0x58): LNK Partner Status (1) ........................................................................................................................ 74 Register 89 (0x59): LNK Partner Status (2) ........................................................................................................................ 74 Register 90 (0x5A): LNK Partner Vendor Info (1)............................................................................................................... 74 Register 91 (0x5B): LNK Partner Vendor Info (2)................................................................................................................ 74 Register 92 ...
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Micrel, Inc. 7 Selection of Isolation Transformer ..............................................................................................99 8 Selection of Crystal/Oscillator.....................................................................................................99 9 Package Information.................................................................................................................100 June 2009 7 hbwhelp@micrel.com KS8993F/FL M9999-062509 or (408) 955-1690 ...
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Micrel, Inc. Table 1: FX and TX Mode Selection.................................................................................................................................................. 26 Table 2: MDI/MDI-X Pin Definition..................................................................................................................................................... 27 Table 3: MII Signals........................................................................................................................................................................... 35 Table 4: SNI (7-wire) Signals............................................................................................................................................................. 35 Table 5: MII Management Interface frame format ............................................................................................................................. 36 Table 6: Serial Management ...
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Micrel, Inc. 1 Signal Description 1.1 KS8993F Pin Diagram 103 PV32 104 PV21 105 PV23 106 DGND 107 VDDIO 108 PV12 109 PV13 110 P3_1PEN 111 P2_1PEN 112 P1_1PEN 113 P3_TXQ2 114 P2_TXQ2 115 P1_TXQ2 116 P3_PP 117 P2_PP 118 ...
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Micrel, Inc. 1.2 Pin Description and I/O Assignment Pin # Pin Name Type 1 P1LED2 I(pu)/O 2 P1LED1 I(pu)/O 3 P1LED0 I(pu)/O 4 P2LED2 I(pu)/O 5 P2LED1 I(pu)/O 6 P2LED0 I(pu)/O 7 DGND Gnd 8 VDDIO Pwr June 2009 Description ...
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Micrel, Inc. Pin # Pin Name Type 9 MCHS Ipd 10 MCCS Ipd 11 PDD# Ipu 12 ADVFC Ipu 13 P2ANEN Ipu 14 P2SPD Ipd 15 P2DPX Ipd 16 P2FFC Ipd 17 P1FST Opu 18 P1LCRCD Ipd June 2009 Description ...
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... Digital ground VDDC : For KS8993F, this is an input power pin for the 1.8V digital core VDD. VOUT_1V8 : For KS8993FL, this is an 1.8V output power pin to supply the KS8993FL’s input power pins: VDDAP (pin 63), VDDC (pins 91, 123) and VDDA (pins 38, 43, 57). ...
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Micrel, Inc. Pin # Pin Name Type 35 DIAGF Ipd 36 PWRDN I 37 AGND Gnd 38 VDDA Pwr 39 AGND Gnd 40 MUX1 I 41 MUX2 I 42 AGND Gnd 43 VDDA Pwr 44 FXSD1 I 45 RXP1 I/O ...
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Micrel, Inc. Pin # Pin Name Type 73 SMTXD2 Ipd 74 SMTXD1 Ipd 75 SMTXD0 Ipd 76 SMTXER Ipd 77 SMTXC Ipd/O 78 DGND Gnd 79 VDDIO Pwr 80 SMRXC Ipd/O 81 SMRXDV O 82 SMRXD3 Ipd/O 83 SMRXD2 Ipd ...
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Micrel, Inc. Pin # Pin Name Type 93 PRSEL0 Ipd 94 MDC Ipu 95 MDIO Ipu/O 96 SPIQ Opu 97 SCL Ipu/O 98 SDA Ipu/O 99 SPIS_N Ipu 100 PS1 Ipd June 2009 Description below to select the desired servicing. ...
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Micrel, Inc. Pin # Pin Name Type 101 PS0 Ipd 102 PV31 Ipu 103 PV32 Ipu 104 PV21 Ipu 105 PV23 Ipu 106 DGND Gnd June 2009 Description registers. [PS1, PS0] = [0, 0] --- I2C master (EEPROM) mode (If ...
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Micrel, Inc. Pin # Pin Name Type 107 VDDIO Pwr 108 PV12 Ipu 109 PV13 Ipu 110 P3_1PEN Ipd 111 P2_1PEN Ipd 112 P1_1PEN Ipd 113 P3_TXQ2 Ipd 114 P2_TXQ2 Ipd 115 P1_TXQ2 Ipd 116 P3_PP Ipd June 2009 Description ...
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Micrel, Inc. Pin # Pin Name Type 117 P2_PP Ipd 118 P1_PP Ipd 119 P3_TAGINS Ipd 120 P2_TAGINS Ipd 121 P1_TAGINS Ipd 122 DGND Gnd 123 VDDC Pwr 124 P3_TAGRM Ipd 125 P2_TAGRM Ipd 126 P1_TAGRM Ipd June 2009 Description ...
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Micrel, Inc. Pin # Pin Name Type 127 TESTEN Ipd 128 SCANEN Ipd Note: Pwr = power supply; Gnd = ground input output; I/O = bi-directional Ipu = input w/ internal pull up; Ipd = input ...
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... The KS8993FL is the single supply version with all the identical rich features of the KS8993F. In the KS8993FL version, pin number 22 provides 1.8V output power to the KS8993FL’s VDDC, VDDA and VDDAP power pins. Refer to the pin description of pin number 22 in section 1.2, Pin Description and I/0 Assignment, for more details. ...
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Micrel, Inc. Bit Command F0-F7 Preamble C0 Conservation Delimiter C1 Direction Delimiter C2-C3 Configuration Delimiter C4-C7 Version C8-C15 Control signal S0 Power S1 Optical S2 UTP link Way for information S5 Loop mode Terminal S6 option Terminal ...
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Micrel, Inc. 2.2.2 MC (Media Converter) Mode MC (Media Converter) mode is selected and configured using hardware pins: MCCS and MCHS. Terminal MC mode without port 3 support is enabled when MCCS=0 and MCHS=1. In this mode, port 1 is ...
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Micrel, Inc. MC loop back operation is initiated and enabled by the center MC. The terminal MC provides the loop back path to return the loop back packet back to the center MC. In terminal MC mode, the KS8993F provides ...
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Micrel, Inc. Pin Signal Name #27 HWPOVR 2.2.6 Port 1 LED Indicator Definition P1LED3 P1LED2 P1LED1 P1LED0 2.2.7 Port 2 LED Indicator Definition P2LED3 P2LED2 P2LED1 P2LED0 June 2009 Type Description Input Hardware pin strapping to override the EEPROM value ...
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Micrel, Inc. 2.3 Physical Transceiver 2.3.1 100BASE-TX Transmit The 100BASE-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ to NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel to serial conversion, which converts the ...
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Micrel, Inc. For 100BASE-FX operation, the KS8993F FXSD1 (fiber signal detect) input pin is usually connected to the fiber transceiver SD (signal detect) output pin. 100BASE-FX mode is activated when FXSD1 is greater than 1V. When FXSD1 is between 1V ...
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Micrel, Inc. 2.3.8 Power Management The KS8993F features a per-port power down mode. To save power, a port that is not being used can be powered down through the port control registers, or MIIM control registers. In addition, there is ...
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Micrel, Inc ...
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Micrel, Inc. 2.3.10 Auto Negotiation The KS8993F conforms to the auto negotiation protocol as described by the 802.3 committee. Auto negotiation allows UTP (Unshielded Twisted Pair) link partners to select the best common mode of operation. In auto negotiation the ...
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Micrel, Inc. 2.4.2 Learning The internal look up engine will update its table with a new entry if the following conditions are met: 1. The received packet's Source Address (SA) does not exist in the look up table. 2. The ...
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Micrel, Inc. Figure 4: Destination Address look up flowchart, stage 1 PTF1 = NULL Search complete. Get PTF1 from Static MAC Table Search complete. Get PTF1 from Dynamic MAC Table June 2009 Start NO VLAN ID valid? YES FOUND Search ...
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Micrel, Inc. Figure 5: Destination Address resolution flowchart, stage 2 Port Mirror Port VLAN Membership June 2009 PTF1 - RX Mirror - TX Mirror Process - Mirror - RX and TX Mirror Check PTF2 32 KS8993F/FL M9999-062509 ...
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Micrel, Inc. The KS8993F will not forward the following packets: 1. Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors. 2. 802.3x pause frames. The KS8993F will intercept these packets and perform the appropriate ...
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Micrel, Inc. On the transmit side, the KS8993F has intelligent and efficient means to determine when to invoke flow control. The flow control is based on the availability of system resources, including available buffers, available transmit queues and available receive ...
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Micrel, Inc. The MII (Media Independent Interface) is specified by the IEEE 802.3 committee and provides a common interface between physical layer and MAC layer devices. The MII Interface provided by the KS8993F is connected to the device’s third MAC. ...
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Micrel, Inc. Transmit enable Serial transmit data Transmit clock Collision detection Carrier sense Serial receive data Receive clock The SNI interface is a bit wide data interface and therefore runs at the network bit rate (not encoded). An additional signal ...
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Micrel, Inc. The Serial Management Interface is the KS8993F non-standard MIIM interface that provides access to all KS8993F configuration registers. This interface allows an external device to completely monitor and control the states of the KS8993F. The SMI interface consists ...
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Micrel, Inc. KS8993F supports “Port Mirroring” comprehensively as: 1) “receive only” mirror on a port All the packets received on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be “receive sniff” and ...
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Micrel, Inc. DA found in Static MAC Use FID flag? Table? No Don’t care No Don’t care Yes Yes Yes Yes FID+SA found in Dynamic MAC Table? No Yes Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non ...
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Micrel, Inc. For split transmit queues, the KS8993F provides four priority schemes: 1. “Transmit all high priority packets before low priority packets”, i.e. a low priority packet could be transmitted only when the high priority queue is empty; 2. “Transmit ...
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Micrel, Inc. Tag insertion is enabled by bit 2 of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. Optionally, the Px_TAGINS strap-in pins can be used to enable this feature. At the egress port, untagged packets ...
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Micrel, Inc. 2 2.10 Master Serial Bus Configuration 2 With an additional I C (“2-wire”) EEPROM, the KS8993F can perform more advanced switch features like “broadcast storm protection” and “rate control” without the need of an external processor. ...
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Micrel, Inc. 2 2.10 Slave Serial Bus Configuration In managed mode, the KS8993F can be configured (external controller/CPU) has complete programming access to the KS8993F’s 128 registers. Programming access includes the Global Registers, Port Registers, ...
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Micrel, Inc. Similarly, SPI multiple write is initiated when the master device continues to drive the KS8993F SPIS_N input pin low after a byte (a register) is written. The KS8993F internal address counter will increment automatically to the next byte ...
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Micrel, Inc. The following four figures illustrate the SPI data cycles for “Write”, “Read”, “Multiple Write” and “Multiple Read”. The read data is registered out of SPIQ on the falling edge of SPIC, and the data input on SPID is ...
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Micrel, Inc. SPIS_N SPIC SPID SPIQ SPIS_N SPIC SPID SPIQ SPIS_N SPIC SPID SPIQ READ COMMAND SPIS_N SPIC SPID SPIQ June 2009 Figure 10: SPI ...
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Micrel, Inc. 3 MII Management (MIIM) Registers The MIIM interface is used to access the MII PHY registers defined in this section. The SPI, I2C and SMI interfaces can also be used to access these registers. The latter three interfaces ...
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Micrel, Inc. Register 1: MII Basic Status Bit Name R capable RO 14 100 Full RO capable 13 100 Half RO capable 12 10 Full RO capable 11 10 Half RO capable 10-7 Reserved RO 6 Preamble RO ...
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Micrel, Inc. Register 4: Auto-Negotiation Advertisement Ability Bit Name R/W 15 Next page RO 14 Reserved RO 13 Remote fault RO 12-11 Reserved RO 10 Pause R/W 9 Reserved R/W 8 Adv 100 Full R/W 7 Adv 100 Half R/W ...
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Micrel, Inc. 4 Register Map: Switch, MC, & PHY (8 bits registers) Global Registers Register Register (Decimal) (Hex) 0-1 0x00 - 0x01 2-11 0x02 - 0x0B 12 0x0C 13-15 0x0D - 0x0F Port Registers Register Register (Decimal) (Hex) 16-29 0x10 ...
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Micrel, Inc. 92 0x5C 93 0x5D 94 0x5E 95 0x5F Advanced Control Registers Register Register (Decimal) (Hex) 96-103 0x60-0x67 104-109 0x68-0x6D 110-111 0x6E-0x6F 112-120 0x70-0x78 121-122 0x79-0x7A 123-124 0x7B-0x7C 125-126 0x7D-0x7E 127 0x7F 4.1 Global Registers Register 0 (0x00): Chip ...
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Micrel, Inc. 3 Pass flow R/W control packet 2 Buffer share R/W mode 1 Reserved R/W 0 Link change R/W age Register 3 (0x03): Global Control 1 Bit Name R/W 7 Pass all R/W frames 6 Repeater R/W Mode 5 ...
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Micrel, Inc. Register 4 (0x04): Global Control 2 Bit Name R/W 7 Unicast R/W port-VLAN mismatch discard 6 Multicast R/W Storm protection Disable 5 Back R/W pressure mode 4 Flow control R/W and back pressure fair mode 3 No excessive ...
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Micrel, Inc. 5 Reserved R/W 4 Reserved R/W 3-2 Priority R/W Scheme select 1 Reserved R/W 0 Sniff mode R./W select Register 6 (0x06): Global Control 4 Bit Name R/W 7 Reserved R/W 6 Switch MII R/W half duplex mode ...
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Micrel, Inc. 10BT 3 Null VID R/W replacement 2-0 Broadcast R/W storm protection rate Bit [10:8] Register 7 (0x07): Global Control 5 Bit Name R/W 7-0 Broadcast R/W storm protection rate Bit [7:0] 100BT Rate: 148,800 frames/sec * 67 ms/interval ...
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Micrel, Inc. 6 PHY power R/W save 5 CRC drop R/W 4 Reserved RW 3 MCLBM1 R/W 2 MCLBM0 R/W 1 LED mode R/W 0 Reserved R/W Register 12 (0x0C): Reserved Register Bit Name R/W 7-0 Reserved Register 13 (0x0D): ...
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Micrel, Inc. Register 14 (0x0E): User Defined Register 2 Bit Name R/W 7-0 UDR2 R/W Register 15 (0x0F): User Defined Register 3 Bit Name R/W 7-0 UDR3 R/W 4.2 Port Registers The following registers are used to enable features that ...
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Micrel, Inc. 1 Tag removal R/W 0 Priority R/W Enable Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Bit Name R/W 7 Sniffer port R/W 6 Receive ...
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Micrel, Inc. 7 Reserved 6 Ingress VLAN R/W filtering 5 Discard Non R/W PVID packets 4 Force flow R/W control 3 Back R/W pressure enable 2 Transmit R/W enable 1 Receive R/W enable 0 Learning R/W disable Register 19 (0x13): ...
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Micrel, Inc. Register 21 (0x15): Port 1 Control 5 Register 37 (0x25): Port 2 Control 5 Register 53 (0x35): Port 3 Control 5 Bit Name R/W 7-0 Transmit high R/W priority rate control [7:0] Register 22 (0x16): Port 1 Control ...
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Micrel, Inc. 3-0 Receive high R/W priority rate control [11:8] Register 27 (0x1B): Port 1 Control 11 Register 43 (0x2B): Port 2 Control 11 Register 59 (0x3B): Port 3 Control 11 Bit Name R/W 7 Receive R/W differential priority rate ...
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Micrel, Inc. 7 Auto R/W Negotiation Enable 6 Force R/W Speed 5 Force R/W duplex 4 Advertised R/W flow control capability 3 Advertised R/W 100BT Full duplex capability 2 Advertised R/W 100BT Half duplex capability 1 Advertised R/W 10BT Full ...
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Micrel, Inc. 6 Txids R/W 5 Restart AN R/W 4 Disable Far- R/W End fault 3 Power down R/W 2 Disable auto R/W MDI/MDI-X 1 Force MDI R/W 0 Reserve R/W Register 30 (0x1E): Port 1 Status 0 Register 46 ...
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Micrel, Inc. 1 Partner 10BT RO Full duplex capability 0 Partner 10BT RO Half duplex capability Register 31 (0x1F): Port 1 Status 1 Register 47 (0x2F): Port 2 Status 1 Register 63 (0x3F): Port 3 Status 1 Bit Name R/W ...
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Micrel, Inc. 4.3 Media Converter Registers Register 64 (0x40): PHY Address Bit Name R/W 7–5 Reserved RO 4 Addr4 R/W 3 Addr3 R/W 2 Addr2 R/W 1 Addr1 R/W 0 Addr0 R/W Register 65 (0x41): Center Side Status Bit Name ...
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Micrel, Inc. Register 66 (0x42): Center Side Command Bit Name R/W Description 7–5 Timer R/W 000 = Reserved (Do Not Use) Delay 001 = 32us (default) 010 = 128us 011 = 256us 100 = 512us 101 = 1ms 110 = ...
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Micrel, Inc reset R reset MC sub-layer, MACs of both PHY ports and switch fabric normal operation 3 Remote R enable “Remote Command” access at Center side and Terminal Command Enable ...
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Micrel, Inc. Register 68 (0x44): Loop Back Setup1 Bit Name R/W Description 7 T7 R/W Center and Terminal sides 6 T6 R/W 0000_0000 : Clear valid transmit and valid receive counters in registers 4Dh R/W ...
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Micrel, Inc. Register 70 (0x46): Loop Back Result Counter for CRC Error Bit Name R/W Description 7 CRC7 RO Center side only 6 CRC6 RO This counter is incremented when loop back packet has CRC error. 5 CRC5 RO 4 ...
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Micrel, Inc. Back Timeout 0 = normal operation 2 CMC Loop Center side is in Loop Back mode too long and the T1 timer has timeout. Back Timeout 0 = normal operation 1 Timeout ...
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Micrel, Inc. Register 76 (0x4C): Remote Command 3 Bit Name R/W Description 7 AMM47 R/W If Center MC sends the “Remote Command” in register 0x42h, this register value will be used for M47-M40 of the Maintenance frame, instead of register ...
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Micrel, Inc. Register 80 (0x50): My Status 1 (Terminal and Center side) Bit Name R/W Description H-MC Link speed H-MC Link Option 1 = Terminal MC mode 0 = Center MC mode 5 ...
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Micrel, Inc. status. For Center MC mode, this bit is always “0” Full Duplex 0 = Half Duplex, or Register 0x50h bit[2] is “1” (UTP link is down For Terminal MC mode, this bit indicates ...
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Micrel, Inc. Register 88 (0x58): LNK Partner Status (1) Bit Name R/W 7-0 LS7–LS0 RO Register 89 (0x59): LNK Partner Status (2) Bit Name R/W 7-0 LS15–LS8 RO Register 90 (0x5A): LNK Partner Vendor Info (1) Bit Name R/W 7-0 ...
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Micrel, Inc. 4.4 Advanced Control Registers The IPv4 TOS priority control registers implement a fully decoded 64 bit DSCP (Differentiated Services Code Point) register used to determine priority from the 6 bit TOS field in the IP header. The most ...
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Micrel, Inc. Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address for MAC pause control frames. Register 104 (0x68): MAC Address Register 0 Bit Name R/W 7-0 MACA[47:40] R/W Register ...
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Micrel, Inc. Register 112 (0x70): Indirect Data Register 8 Bit Name R/W 68-64 Indirect data R/W Register 113 (0x71): Indirect Data Register 7 Bit Name R/W 63-56 Indirect data R/W Register 114 (0x72): Indirect Data Register 6 Bit Name R/W ...
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Micrel, Inc. 7-0 Factory RO testing Register 123 (0x7B): Digital Testing Control 0 Bit Name R/W 7-0 Factory R/W testing Register 124 (0x7C): Digital Testing Control 1 Bit Name R/W 7-0 Factory R/W testing Register 125 (0x7D): Analog Testing Control ...
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Micrel, Inc. Bit Name 57-54 FID 53 Use FID 52 Override 51 Valid 50-48 Forwarding ports 47-0 MAC address Examples: 1) Static Address Table Read (read the 2 Write to reg. 110 with 0x10 (read static table selected) Write to ...
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Micrel, Inc. VLAN table is used to do VLAN table look up. If 802.1Q VLAN mode is enabled (Register 5, Bit 7 = 1), this table will be used to retrieve the VLAN information that is associated with the ingress ...
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Micrel, Inc. Bit Name 71 Data not ready 70-67 Reserved 66 MAC empty 65- valid entries 55-54 Time Stamp 53-52 Source port 51-48 FID 47-0 MAC Address Example: Dynamic MAC Address Table Read (read the 1 Write to ...
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Micrel, Inc. Bit Name 31 Reserve 30 Count Valid 29-0 Counter Values “Per Port” MIB Counters are read using indirect memory access. The base address offsets and address ranges for all three ports are: Port 1 : base is 0x00 ...
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Micrel, Inc. 0xB RxBroadcast 0xC RxMulticast 0xD RxUnicast 0xE Rx64Octets 0xF Rx65to127Octets 0x10 Rx128to255Octets 0x11 Rx256to511Octets 0x12 Rx512to1023Octets 0x13 Rx1024to1522Octets 0x14 TxLoPriorityByte 0x15 TxHiPriorityByte 0x16 TxLateCollision 0x17 TxPausePkts 0x18 TxBroadcastPkts 0x19 TxMulticastPkts 0x1A TxUnicastPkts 0x1B TxDeferred 0x1C TxTotalCollision 0x1D TxExcessiveCollision ...
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Micrel, Inc. 0x1E TxSingleCollision 0x1F TxMultipleCollision Table 15: Format of “All Port Dropped Packet” MIB Counters Bit Name 30-16 Reserved 15-0 Counter values “All Port Dropped Packet” MIB Counters are read using indirect memory access. The address offsets for these ...
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Micrel, Inc. Write to reg. 110 with 0x1d (read MIB counter selected) Write to reg. 111 with 0x00 (trigger the read operation) Then Read reg. 119 (counter value 15-8) Read reg. 120 (counter value 7-0) NOTES: 1. Both “Per Port” ...
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Micrel, Inc. 5 Electrical Specifications Stresses greater than those listed in this table may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification ...
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Micrel, Inc. 5.3 Electrical Characteristics Parameter Supply Current (including TX output driver current for KS8993F device only) 100BASE-TX operation (total) 100BASE- 10BASE-T operation (total) 10BASE 100BASE-TX (analog 100BASE-TX (digital 10BASE-T(analog ...
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Micrel, Inc. 10BASE-T Transmit (measured differentially after 1:1 transformer Peak Differential Output V p Voltage Jitters Added Rise/Fall time 5.4 100BASE-FX Electrical Specification Parameter Sym Supply Current (including FX output driver current) 100BASE-FX operation - total 100BASE-FX (transmitter ...
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Micrel, Inc. 6 Timing Specifications 6.1 EEPROM Timing Receive Timing SCL SDA Transmit Timing SCL SDA Timing Description Parameter tcyc1 Clock cycle ts1 Setup time th1 tov1 Output Valid June 2009 Figure 12: EEPROM Interface Input Timing Diagram ts1 tcyc1 ...
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Micrel, Inc. 6.2 SNI Timing Receive Timing MTXC MTXEN MTXD[0] Transmit Timing MRXC MRXDV MCOL MRXD[0] Timing Description Parameter tcyc2 Clock cycle ts2 Setup time th2 tov2 Output Valid June 2009 Figure 14: SNI Input Timing Diagram ts2 tcyc2 Figure ...
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Micrel, Inc. 6.3 MII Timing 6.3.1 MAC Mode MII Timing Figure 16: MAC Mode MII Timing - Data received from MII Receive Timing MRXCLK MTXEN MTXER MTXD[3:0] Figure 17: MAC Mode MII Timing - Data transmitted to MII Transmit Timing ...
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Micrel, Inc. 6.3.2 PHY Mode MII Timing Figure 18: PHY Mode MII Timing – Data received from MII Receive Timing MTXCLK MTXEN MTXER MTXD[3:0] Figure 19: PHY Mode MII Timing - Data transmitted to MII Transmit Timing MRXCLK MRXDV MRXD[3:0] ...
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Micrel, Inc. SPIS_N tCHSL SPIC tDVCH SPID SPIQ Timing Description Parameter fC Clock Frequency tCHSL SPIS_N Inactive Hold Time tSLCH SPIS_N Active Setup Time tCHSH SPIS_N Active Hold Time tSHCH SPIS_N Inactive Setup Time tSHSL SPIS_N Deselect Time tDVCH Data ...
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Micrel, Inc. SPIS_N SPIC tCLQX SPIQ SPID Timing Description Parameter fC Clock Frequency tCLQX SPIQ Hold Time tCLQV Clock Low to SPIQ Valid tCH Clock High Time tCL Clock Low Time tQLQH SPIQ Rise Time tQHQL SPIQ Fall Time tSHQZ ...
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Micrel, Inc. 6.3.4 MDC/MDIO Timing Figure 22: MDC/MDIO Timing for MIIM and SMI Interfaces MDC MDIO (Into Chip) MDIO (Out of Chip) t MDC period P t MDC pulse width WL t MDC pulse width WH t MDIO Setup to ...
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Micrel, Inc. 6.3.5 Auto Negotiation Timing TX+/TX- TX+/TX- t FLP burst to FLP burst BTB t FLP burst width FLPW t Clock/Data pulse width PW t Clock pulse to data pulse CTD t Clock pulse to clock pulse CTC Number ...
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Micrel, Inc. Reset Timing 6.4 The KS8993F should be powered up with the VDD core voltages applied before the VDDIO voltage. In the worst case, both VDD core and VDDIO voltages can be applied simultaneously. Additional, reset timing requirement are ...
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Micrel, Inc. 6.5 Reset Circuit The reset circuit in is recommended for powering up the KS8993F if reset is triggered only by the power supply. Figure 25 KS8993F The reset circuit in is recommended for applications where reset is driven ...
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Micrel, Inc. 7 Selection of Isolation Transformer An 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. characteristics. Parameter Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) ...
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Micrel, Inc. 9 Package Information MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and ...