KS8995MAL Micrel Inc, KS8995MAL Datasheet - Page 50

• Manufacturer Part Number: KS8995MAL
• Description: IC SWITCH 10/100 5PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8995MAL

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• For Use With: 576-1017 - BOARD EVAL EXPERIMENT KS8995M
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

KS8995MA
Advanced Control Registers
The IPv4 TOS priority control registers implement a fully decoded 64 bit differentiated services code point (DSCP) register used
to determine priority from the 6 bit TOS field in the IP header. The most significant 6 bits of the TOS field are fully decoded into
64 possibilities, and the singular code that results is compared against the corresponding bit in the DSCP register. If the register
bit is a 1, the priority is high; if the register bit is a 0, the priority is low.
Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address in MAC pause control frames.
M9999-051305
Register 31 (0x1F): Port 1 Control 14
Register 47 (0x2F): Port 2 Control 14
Register 63 (0x3F): Port 3 Control 14
Register 79 (0x4F): Port 4 Control 14
Register 95 (0x5F): Port 5 Control 14
Address
7
6
5
4
3
2-1
0
Address
Register 96 (0x60): TOS Priority Control Register 0
7-0
Register 97 (0x61): TOS Priority Control Register 1
7-0
Register 98 (0x62): TOS Priority Control Register 2
7-0
Register 99 (0x63): TOS Priority Control Register 3
7-0
Register 100 (0x64): TOS Priority Control Register 4
7-0
Register 101 (0x65): TOS Priority Control Register 5
7-0
Register 102 (0x66): TOS Priority Control Register 6
7-0
Register 103 (0x67): TOS Priority Control Register 7
7-0
Register 104 (0x68): MAC Address Register 0
7-0
Register 105 (0x69): MAC Address Register 1
7-0
Name
PHY Loopback
Remote Loopback
PHY Isolate
Soft Reset
Force Link
Reserved
Far End Fault
Name
DSCP[63:56]
DSCP[55:48]
DSCP[47:40]
DSCP[39:32]
DSCP[31:24]
DSCP[23:16]
DSCP[15:8]
DSCP[7:0]
MACA[47:40]
MACA[39:32]
Description
1, perform PHY loopback, i.e. loopback MAC’s Tx
back to Rx.
0, normal operation.
1, perform remote loopback, i.e. loopback PHY’s Rx
back to Tx.
0, normal operation.
1, electrical isolation of PHY from MII and Tx+/Tx-.
0, normal operation.
1, PHY soft reset.
0, normal operation.
1, Force link in the PHY.
0, normal operation.
N/A
1, Far end fault status detected.
0, no far end fault status detected.
Description
50
Mode
R/W
R/W
R/W
R/W
R/W
RO
RO
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
Default
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
0x00
0x10
Micrel, Inc.
May 2005