KS8842-16MQL Micrel Inc, KS8842-16MQL Datasheet - Page 70
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KS8842-16MQL
Manufacturer Part Number
KS8842-16MQL
Description
IC SWITCH 10/100 16BIT 128PQFP
Manufacturer
Micrel Inc
Specifications of KS8842-16MQL
Applications
*
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Number Of Primary Switch Ports
2
Internal Memory Buffer Size
32
Operating Supply Voltage (typ)
3.3V
Fiber Support
Yes
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII
Power Supply Type
Analog/Digital
Package Type
PQFP
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.5V
Operating Supply Voltage (min)
3.1V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
KS8842-PMQL-EVAL - EVAL KIT EXPERIMENTAL KS8842KS8842-16MQL-EVAL - EVAL KIT EXPERIMENTAL KS8842
Lead Free Status / RoHS Status
Not Compliant, Lead free / RoHS Compliant
Other names
576-1458
Available stocks
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Part Number
Manufacturer
Quantity
Price
Bank 18 Interrupt Status Register (0x02): ISR
This register contains the status bits for all QMU and other interrupt sources.
When the corresponding enable bit is set, it causes the interrupt pin to be asserted.
This register is usually read by the host CPU and device drivers during interrupt service routine or polling. The register bits
are not cleared when read. The user has to write “1” to clear
Micrel, Inc.
Bit
15
14
13
12
11
10
9
8
7
6-0
October 2007
Default Value
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x1
0x0
-
R/W
RO
(W1C)
RO
(W1C)
RO
(W1C)
RO
RO
(W1C)
RO
RO
(W1C)
RO
(W1C)
RO
(W1C)
RO
Description
LCIS Link Change Interrupt Status
When this bit is set, it indicates that the link status has changed from link up to link
down, or link down to link up.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
TXIS Transmit Status
When this bit is set, it indicates that the TXQ MAC has transmitted at least a frame on
the MAC interface and the QMU TXQ is ready for new frames from the host.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXIS Receive Interrupt Status
When this bit is set, it indicates that the QMU RXQ has received a frame from the
MAC interface and the frame is ready for the host CPU to process.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
Reserved
RXOIS Receive Overrun Interrupt Status
When this bit is set, it indicates that the Receive Overrun status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
Reserved
TXPSIE Transmit Process Stopped Status
When this bit is set, it indicates that the Transmit Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXPSIE Receive Process Stopped Status
When this bit is set, it indicates that the Receive Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXEFIE Receive Error Frame Interrupt Status
When this bit is set, it indicates that the Receive error frame status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
Reserved
70
KSZ8842-16/32 MQL/MVL/MVLI/MBL
M9999-102207-1.9