KS8999I Micrel Inc, KS8999I Datasheet
KS8999I
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KS8999I Summary of contents
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... The KS8999 is designed to reside in an unmanaged design not requiring processor intervention. Functional Diagram Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com January 2005 KS8999 Integrated 9-Port 10/100 Switch with PHY and Frame Buffer Rev 1 ...
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... Industrial temperature range: –40°C to +85°C (KSZ8999I) • Available in 208-pin PQFP package Ordering Information Part Number Temp Range KS8999 0°C to +70°C KS8999I –40°C to +85°C KSZ8999 0°C to +70°C KSZ8999I –40°C to +85°C 2 KS8999 Package 208-Pin PQFP ...
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... Correct pin 174 and 175 description 1.09 6/18/02 Correct default to floating for pin 174 Change pin 87 TEST[3] to AUTOMDIX for enable/disable of auto MDI-MDIX function 1.10 2/27/03 Add KS8999I industrial temperature Update non-periodic blinking in Mode 1 of LED[1:9][0] Add MRXD[0] description 1.11 5/12/03 Changed V 1.12 8/29/03 Convert to new format ...
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Micrel, Inc. Contents System Level Applications.............................................................................................................................................6 Pin Configuration ............................................................................................................................................................7 Pin Description ................................................................................................................................................................8 I/O Grouping ..................................................................................................................................................................14 I/O Description...............................................................................................................................................................14 Functional Overview: Physical Layer Transceiver ....................................................................................................19 100BaseTX Transmit ................................................................................................................................................19 100BaseTX Receive .................................................................................................................................................19 PLL Clock Synthesizer..............................................................................................................................................19 Scrambler/De-scrambler (100BaseTX only).............................................................................................................19 100BaseFX Operation ..............................................................................................................................................19 100BaseFX Signal ...
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Micrel, Inc. EEPROM Memory Map..................................................................................................................................................29 General Control Register ..........................................................................................................................................29 Priority Classification Control –802.1p tag field ........................................................................................................29 Port 1 Control Register .............................................................................................................................................29 Port 2 Control Register .............................................................................................................................................30 Port 3 Control Register .............................................................................................................................................30 Port 4 Control Register .............................................................................................................................................30 Port 5 Control Register ...
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Micrel, Inc. System Level Applications The KS8999 can be configured to fit either in an eight port 10/100 application nine port 10/100 network interface with an extra MII/7-wire port. This MII/7-wire port can be connected to an ...
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Micrel, Inc. Pin Configuration January 2005 208-Pin PQFP (PQ) 7 KS8999 KS8999 ...
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Micrel, Inc. Pin Description Pin Number Pin Name 1 VDD_RX 2 GND_RX 3 GND_RX 4 VDD_RX 5 RXP[3] 6 RXM[3] 7 AOUT2 8 DOUT2 9 TXP[3] 10 TXM[3] 11 QH[5] 12 QH[4] 13 QH[3] 14 QH[2] 15 GND_TX 16 VDD_TX ...
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Micrel, Inc. Pin Number Pin Name 39 QL[2] 40 QL[3] 41 QL[4] 42 QL[5] 43 TXP[6] 44 TXM[6] 45 DOUT 46 AOUT 47 RXP[6] 48 RXM[6] 49 VDD_RX 50 GND_RX 51 GND_RX 52 VDD_RX 53 GND-ISO 54 RXP[7] 55 RXM[7] ...
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Micrel, Inc. Pin Number Pin Name 78 VDD_RCV 79 VDD_RCV 80 BTOUT2 81 CTOUT2 82 RLPBK 83 MUX[1] 84 MUX[2] 85 TEST[1] 86 TEST[2] 87 AUTOMDIX 88 T[1] 89 T[2] 90 T[3] 91 EN1P 92 SDA 93 SCL 94 VDD ...
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Micrel, Inc. Pin Number Pin Name 117 LED[2][1] 118 LED[2][0] 119 MRXDV 120 MRXD[3] 121 MRXD[2] 122 MRXD[1] 123 MRXD[0] 124 MRXC 125 VDD-IO 126 GND 127 LED[3][3] 128 LED[3][2] 129 LED[3][1] 130 LED[3][0] 131 LED[4][3] 132 LED[4][2] 133 LED[4][1] ...
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Micrel, Inc. Pin Number Pin Name 156 IO_SWM 157 VDD 158 LED[9][3] 159 LED[9][2] 160 LED[9][1] 161 LED[9][0] 162 MIIS[1] 163 MIIS[0] 164 MODESEL[3] 165 MODESEL[2] 166 MODESEL[1] 167 MODESEL[0] 168 TESTEN 169 SCANEN 170 PRSV 171 CFGMODE 172 T[5] ...
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Micrel, Inc. Pin Number Pin Name 195 GND_RX 196 RXP[1] 197 RXM[1] 198 GND_TX 199 TXP[1] 200 TXM[1] 201 VDD_TX 202 VDD_TX 203 TXP[2] 204 TXM[2] 205 GND_TX 206 RXP[2] 207 RXM[2] 208 GND-ISO Notes Power supply. ...
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Micrel, Inc. I/O Grouping Group Name Description PHY Physical Interface MII Media Independent Interface SNI Serial Network Interface IND LED Indicators UP Unmanaged Programmable CTRL Control and Miscellaneous TEST Test (Factory) PWR Power and Ground I/O Descriptions Group I/O Names ...
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Micrel, Inc. Group I/O Names Active Status LED[1:9][2] LED[1:9][3] UP MODESEL[3:0] LED[1][3] LED[1][2] LED[1][1] LED[1][0] January 2005 Description L Output (after reset) Mode 0: Collision (on = collision/off = no collision) Mode 1: Transmit Activity (on during transmission) Mode 2: ...
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Micrel, Inc. Group I/O Names Active Status LED[2][3] LED[2][2] LED[2][1] LED[2][0] LED[3][3] LED[3][2] LED[3][1] LED[3][0] LED[4][3] LED[4][2] LED[4][1] LED[4][0] LED[5][3] LED[5][2] LED[5][1] LED[5][0] LED[9][3] LED[9][2] LED[9][1] LED[9][0] LED[6][3] LED[6][2] LED[6][1:0] January 2005 Description Programs auto-negotiation on port ...
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Micrel, Inc. Group I/O Names Active Status LED[7][3] LED[7][2] LED[7][1] LED[7][0] LED[8][3] LED[8][2] LED[8][1] LED[8][0] MRXD[3] MRXD[2] MRXD[1] MRXD[0] CTRL EN1P MIIS[1:0] PRSV CFGMODE X1 X2 SCL SDA RST# TEST TESTEN SCANEN MUX[1:2] AOUT January 2005 Description Programs flow control ...
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Micrel, Inc. Group I/O Names Active Status DOUT AOUT2 DOUT2 BTOUT CTOUT BTOUT2 CTOUT2 TEST[1:2] AUTOMDIX T[1:3] & T[5] T[4] QH[2:5] QL[2:5] IO_SWM RLPBK BIST PWR VDD_RX GND_RX VDD_TX GND_TX VDD_RCV GND_RCV VDD_PLLTX GND_PLLTX GND-ISO VDD VDD-IO GND Note: 1. ...
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Micrel, Inc. Functional Overview: Physical Layer Transceiver 100BaseTX Transmit The 100BaseTX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ to NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel to serial conversion, which converts ...
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Micrel, Inc. and a PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulse widths in order to prevent ...
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Micrel, Inc. Functional Overview: Switch Core Address Look-Up The internal look-up table stores MAC addresses and their associated information. It contains 1K full CAM with 48-bit address plus switching information. The KS8999 is guaranteed to learn 1K addresses and distinguishes ...
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Micrel, Inc. MAC Operation The KS8999 strictly abides by IEEE 802.3 standard to maximize compatibility. Inter Packet Gap (IPG frame is successfully transmitted, the 96 bit time IPG is measured between the two consecutive MTXEN. If the current ...
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Micrel, Inc. MII Interface Operation The MII (Media Independent Interface) operates in either a MAC or PHY mode. In the MAC mode, the KS8999 MII acts like a MAC and in the PHY mode, it acts like a PHY device. ...
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Micrel, Inc. Note that the signal MRXER is not provided on the MII interface for the KS8999 for PHY mode operation and MTXER is not represented for MAC mode. Normally this would indicate a receive / transmit error coming from ...
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Micrel, Inc. SNI Interface (7-wire) Operation The SNI (Serial Network Interface) is compatible with some controllers used for network layer protocol processing. KS8999 acts like a PHY device to external controllers. This interface can be directly connected to these types ...
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Micrel, Inc. is Priority Control Scheme (register 2 bits 2-3) which controls the interleaving of high and low priority frames. Options allow from a 2:1 ratio setting that sends all the high priority first. This setting controls ...
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Micrel, Inc. The table below briefly summarizes VLAN features. For more detailed settings see the EEPROM register description. Register(s) Bit(s) Global/Port 4-12 2 Port 4-12 1 Port 2 0 Global 13-21 7-0 Port 22-39 7-0 Port Station MAC Address (control ...
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Micrel, Inc. Optional CPU Interface Instead of using an EEPROM to program the KS8999, one can use an external processor. To utilize this feature, the CFGMODE pin (only available on the 208 pin package) needs to pulled low. This makes ...
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Micrel, Inc. EEPROM Memory Address Name Description 0 7-0 Signature byte 1. Value = “55” 1 7-0 Signature byte 2. Value = “99” General Control Register 2 7-4 Reserved –set to zero 2 3-2 Priority control scheme (all ports) 00 ...
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Micrel, Inc. Address Name Description Port 2 Control Register 5 7-6 Reserved –set to zero 5 5 TOS priority classification enable for port Enable 0 = Disable 5 4 802.1p priority classification enable for port 2 1 ...
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Micrel, Inc. Address Name Description 7 1 Strip VLAN tags for port 4 if existent 1 = Enable 0 = Disable 7 0 Enable high and low output priority queues for port Enable 0 = Disable Port ...
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Micrel, Inc. Address Name Description 10 3 Port based priority classification for port High priority 0 = Low priority 10 2 Insert VLAN tags for port 7 if non-existent 1 = Enable 0 = Disable 10 1 ...
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Micrel, Inc. Address Name Description 13 6 Port 8 inclusion 1 = Port 8 in the same VLAN as port Port 8 not in the same VLAN as port Port 7 inclusion 1 = ...
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Micrel, Inc. Address Name Description 15 4 Port 6 inclusion 1 = Port 6 in the same VLAN as port Port 6 not in the same VLAN as port Port 5 inclusion 1 = ...
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Micrel, Inc. Address Name Description 17 2 Port 3 inclusion 1 = Port 3 in the same VLAN as port Port 3 not in the same VLAN as port Port 2 inclusion 1 = ...
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Micrel, Inc. Address Name Description 19 0 Port 1 inclusion 1 = Port 1 in the same VLAN as port Port 1 not in the same VLAN as port 7 Port 8 VLAN Mask Register 20 7 ...
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Micrel, Inc. Address Name Description 22 3-0 VID [11:8] 23 7-0 VID [7:0] Port 2 VLAN Tag Insertion Value Registers 24 7-5 User priority [2: CFI 24 3-0 VID [11:8] 25 7-0 VID [7:0] Port 3 VLAN Tag ...
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Micrel, Inc. Address Name Description Port 9 VLAN Tag Insertion Value Registers 38 7-5 User priority [2: CFI 38 3-0 VID [11:8] 39 7-0 VID [7:0] Diff Serv Code Point Registers 40 7-0 DSCP[63:56] 41 7-0 DSCP[55:48] 42 ...
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Micrel, Inc. Absolute Maximum Ratings Supply Voltage ( RX, DD TX, DD RCV, DD ....................................... –0.5V to +2.3V DD PLLTX ............................................. –0.5V to +3.8V DDIO Input Voltage ......................................... ...
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Micrel, Inc. Symbol Parameter 100BaseTX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion Overshoot Reference Voltage of ISET V SET Output Jitters 10BaseTX Receive Squelch Threshold V SQ 10BaseT Transmit (measured differentially after 1:1 transformer) Peak Differential Output Voltage ...
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Micrel, Inc. Timing Diagrams Symbol Parameter t Clock Cycle CYC t Set-Up Time S t Hold Time H Symbol Parameter t Clock Cycle CYC t Output Valid OV January 2005 Figure 7. EEPROM Input Timing Min 16384 20 20 Table ...
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Micrel, Inc. Symbol Parameter t Clock Cycle CYC t Set-Up Time S t Hold Time H Symbol Parameter t Clock Cycle CYC t Output Valid OV January 2005 Figure 9. SNI (7-wire) Input Timing Min 10 0 Table 7. SNI ...
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Micrel, Inc. Figure 11. KS8999 PHY Mode―Data Sent from External MAC Controller to KS8999 Symbol Parameter t Clock Cycle (100BaseT) CYC t Clock Cycle (10BaseT) CYC t Set-Up Time S T Hold Time H Table 9. MII Timing in KS8999 ...
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Micrel, Inc. Figure 13. KS8999 PHY Mode―Data Sent from KS8999 PHY Mode to External MAC Controller Symbol Parameter t Clock Cycle (100BaseT) CYC t Clock Cycle (10BaseT) CYC t Output Valid OV Table 10. KS8999 PHY Mode Transmit Timing Parameters ...
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Micrel, Inc. Figure 15. KS8999 MAC Mode―Data Sent from External PHY Device to KS8999 Symbol Parameter t Clock Cycle (100BaseT) CYC t Clock Cycle (10BaseT) CYC t Output Valid S t Output Valid H Table 11. KS8999 PHY Mode Transmit ...
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Micrel, Inc. Figure 17. KS8999 MAC Mode Timing―Data Sent from KS8999 MAC mode to External PHY Device Symbol Parameter t Clock Cycle (100BaseT) CYC t Clock Cycle (10BaseT) CYC t Output Valid OV Table 12. KS8999 MAC Mode Transmit Timing ...
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Micrel, Inc. Reference Circuits See “I/O Description” section for pull-up/pull-down and float information. Reset Reference Circuit Micrel recommended the following discrete reset circuit as shown in Figure 20 when powering up the KS8999 device. For the application where the reset ...
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Micrel, Inc. Figure 21. Recommended Circuit for Interfacing with CPU/FPGA Reset At power-on-reset and D1 provide the necessary ramp rise time to reset the KS8999 device. The reset out from CPU/FPGA provides warm reset after power up. It ...
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Micrel, Inc. 4B/5B Coding In 100BaseTX and 100BaseFX the data and frame control are encoded in the transmitter (and decoded in the receiver) using a 4B/5B code. The extra code space is required to encode extra control (frame delineation) points. ...
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Micrel, Inc. MLT3 Coding For 100BaseTX operation the NRZI (Non-Return to Zero Invert on ones) signal is line coded as MLT3. The net result of using MLT3 is to reduce the EMI (Electro Magnetic Interference) of the signal over twisted ...
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Micrel, Inc. Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common- mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name ...
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Micrel, Inc. Package Information January 2005 208-Pin PQFP (PQ) 52 KS8999 KS8999 ...
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Micrel, Inc. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no ...