HCPL-3700-000E Avago Technologies US Inc., HCPL-3700-000E Datasheet - Page 9

• Manufacturer Part Number: HCPL-3700-000E
• Description: OPTOCOUPLER AC/DC LOGIC 8DIP
• Manufacturer: Avago Technologies US Inc.
• Type: Analogr

Specifications of HCPL-3700-000E

• Output Type: Open Collector
• Package / Case: 8-DIP (0.300", 7.62mm)
• Voltage - Isolation: 3750Vrms
• Number Of Channels: 1, Unidirectional
• Current - Output / Channel: 30mA
• Propagation Delay High - Low @ If: 4µs
• Current - Dc Forward (if): 50mA
• Input Type: Logic
• Mounting Type: Through Hole
• Logic Gate Type: AC / DC to Logic Interface Optocouplers
• Configuration: 1 Channel
• Isolation Voltage: 3750 Vrms
• Maximum Propagation Delay Time: 40000 ns
• Maximum Forward Diode Voltage: 50 mA
• Maximum Forward Diode Current: 4.4 mA
• Maximum Continuous Output Current: 30 mA
• Maximum Power Dissipation: 305 mW
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package Type: 8-Pin DIP
• No. Of Channels: 1
• Optocoupler Output Type: Photodarlington
• Input Current: 3.7mA
• Output Voltage: 20V
• Opto Case Style: DIP
• No. Of Pins: 8
• Common Mode Ratio: 4000
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 516-1545-5

Notes:
10. The t
11. The t
12. Common mode transient immunity in Logic High level is the maximum tolerable (positive) dV
13. In applications where dV
14. Logic low output level at Pin 6 occurs under the conditions of V
15. AC voltage is instantaneous voltage.
16. Device considered a two terminal device: Pins 1, 2, 3, 4 connected together, and Pins 5, 6, 7, 8 connected together.
17. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 4500 V rms for 1 second (leakage detection
18. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 6000 V rms for 1 second (leakage detection current
Figure 1. Typical input characteristics, I
V
9
9. All typical values are at T
1. Measured at a point 1.6 mm below seating plane.
2. Current into/out of any single lead.
3. Surge input current duration is 3 ms at 120 Hz pulse repetition rate. Transient input current duration is 10 s at 120 Hz pulse repetition rate. Note that
4. Derate linearly above 70 C free-air temperature at a rate of 4.1 mW/ C (HCPL-3700/3760) and 3.1 mW/ C (HCPL-0370). Maximum input power
5. Derate linearly above 70 C free-air temperature at a rate of 5.4 mW/ C (HCPL-3700/3760) and 5 mW/ C (HCPL-0370).
6. Derate linearly above 70 C free-air temperature at a rate of 3.9 mW/ C (HCPL-3700/3760) and 1.9 mW/ C (HCPL-0370). Maximum output power
7. Derate linearly above 70 C free-air temperature at a rate of 0.6 mA/ C.
8. Maximum operating frequency is defined when output waveform Pin 6 obtains only 90% of V
IN
(AC voltage is instantaneous value).
maximum input power, P
dissipation of 230 mW (HCPL-3700/3760) and 172 mW (HCPL-0370) allows an input IC junction temperature of 125 C at an ambient temperature of
T
dissipation of 210 mW (HCPL-3700/3760) and 103 mW (HCPL-0370) allows an output IC junction temperature of 125 C at an ambient temperature of
T
input signal.
edge of the output pulse (see Figure 10).
edge of the output pulse (see Figure 10).
V
tolerable (negative) dV
(i.e., V
from destructively high surge currents. The recommended value for R
minimum value of 240 .
output level at Pin 6 occurs under the conditions of V
current limit, I
limit, I
Insulation Characteristics Table.
A
A
CM
= 70 C. Excessive P
= 70 C.
, to insure that the output will remain in a Logic High state (i.e., V
PHL
PLH
O
i-o
< 0.8 V). See Figure 11.
propagation delay is measured from the 2.5 V level of the leading edge of a 5.0 V input pulse (1 s rise time) to the 1.5 V level on the leading
propagation delay is measured from the 2.5 V level of the trailing edge of a 5.0 V input pulse (1 s fall time) to the 1.5 V level on the trailing
5 A). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN 60747-5-2
i-o
5 A).
CM
IN
CM
IN
/dt on the trailing edge of the common mode pulse signal, V
and T
A
, must be observed.
= 25 C, V
/dt may exceed 50,000 V/ s (such as static discharge), a series resistor, R
J
may result in IC chip degradation.
CC
IN
= 5.0 V unless otherwise stated.
vs.
Figure 2. Typical transfer characteristics.
IN
V
TH-
as well as the range of V
IN
V
O
TH+
CC
> 2.0 V). Common mode transient immunity in Logic Low level is the maximum
is 240
as well as the range of V
per volt of allowable drop in V
CM
IN
, to insure that the output will remain in a Logic Low state
< V
CM
CC
TH+
/dt on the leading edge of the common mode pulse,
with R
once V
IN
> V
L
CC
= 4.7 k , C
V
V
TH–
IN
, should be included to protect the detector IC
TH(dc)
TH(ac)
I
TH
has decreased below V
once V
HCPL-0370/3700
CC
HCPL-3760
(between Pin 8 and V
IN
DEVICE
L
ALL
ALL
= 30 pF using a 5 V square wave
has exceeded V
2.5 mA
1.2 mA
3.7 V
4.9 V
TH
TH-
+
.
TH+
CC
1.3 mA
0.6 mA
. Logic high
2.6 V
3.7 V
TH
) with a
–
CONNNECTION
PINS 2, 3
PINS 2, 3
PINS 1, 4
OR 1, 4
INPUT