HCPL-0738 Avago Technologies US Inc., HCPL-0738 Datasheet - Page 7

• Manufacturer Part Number: HCPL-0738
• Description: OPTOCOUPLER CMOS 15MBD 8-SOIC
• Manufacturer: Avago Technologies US Inc.

Specifications of HCPL-0738

• Voltage - Isolation: 3750Vrms
• Number Of Channels: 2, Unidirectional
• Current - Output / Channel: 2mA
• Data Rate: 15MBd
• Propagation Delay High - Low @ If: 35ns @ 12mA
• Current - Dc Forward (if): 20mA
• Input Type: DC
• Output Type: Open Collector
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• No. Of Channels: 2
• Isolation Voltage: 3.75kV
• Optocoupler Output Type: Logic Gate
• Input Current: 16mA
• Output Voltage: 5V
• Opto Case Style: SOIC
• No. Of Pins: 8
• Propagation Delay Low-high: 60ns
• Common Mode Voltage Vcm: 1000V
• Number Of Elements: 2
• Baud Rate: 15Mbps
• Forward Voltage: 1.8V
• Forward Current: 20mA
• Output Current: 2mA
• Package Type: SOIC
• Operating Temp Range: -40C to 100C
• Propagation Delay Time: 60ns
• Pin Count: 8
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 516-1117-5

Propagation Delay, Pulse-Width
Distortion, and Propagation Delay Skew
Propagation delay is a figure of merit which describes how
quickly a logic signal propagates through a system. The
propagation delay from low to high (t
of time required for an input signal to propagate to the
output, causing the output to change from low to high.
Similarly, the propagation delay from high to low
(t
put signal to propagate to the output, causing the
output to change from high to low (see Figure 7).
Pulse-width distortion (PWD) results when t
t
between t
mum data rate capability of a transmission system. PWD
Figure 6. Recommended printed circuit board layout.
7
Application Information
Bypassing and PC Board Layout
The HCPL-0738 optocoupler is extremely easy to use. No
external interface circuitry is required because the HCPL-
0738 uses high-speed CMOS IC technology allowing CMOS
logic to be connected directly to the inputs and outputs.
PHL
GND 1
GND 1
PHL
I
I
F1
F2
differ in value. PWD is defined as the difference
) is the amount of time required for the in-
PLH
and t
1
2
3
4
PHL
and often determines the maxi-
7
6
8
5
PLH
) is the amount
GND 2
C
PLH
V
V
V
DD
O
O
and
1
2
As shown in Figure 6, the only external component required
for proper operation is the bypass capacitor. Capacitor values
should be between 0.01 µF and 0.1 µF. For each capacitor,
the total lead length between both ends of the capacitor
and the power-supply pins should not exceed 20 mm.
can be expressed in percent by dividing the PWD (in ns)
by the minimum pulse width (in ns) being transmitted.
Typically, PWD on the order of 20-30% of the minimum
pulse width is tolerable; the exact figure depends on
the particular application (RS232, RS422, T-1, etc.).
Propagation delay skew, t
to con-sider in parallel data applications where synchro-
nization of signals on parallel data lines is a concern. If
the parallel data is being sent through a group of op-
tocouplers, differences in propagation delays will cause
the data to arrive at the outputs of the optocouplers at
different times. If this difference in propagation delays
is large enough, it will determine the maximum rate at
which parallel data can be sent through the optocouplers.
PSK
, is an important parameter