6N138(TP1,F) Toshiba, 6N138(TP1,F) Datasheet - Page 4

• Manufacturer Part Number: 6N138(TP1,F)
• Description: PHOTOCOUPLER DUAL DARL 8-DIP
• Manufacturer: Toshiba

Specifications of 6N138(TP1,F)

• Voltage - Isolation: 2500Vrms
• Number Of Channels: 1, Unidirectional
• Current - Output / Channel: 60mA
• Propagation Delay High - Low @ If: 1µs @ 1.6mA
• Current - Dc Forward (if): 20mA
• Input Type: DC
• Output Type: Logic
• Mounting Type: Surface Mount
• Package / Case: 8-SMD (300 mil)
• Voltage - Output: 18V
• Current Transfer Ratio (min): 300% @ 1.6mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Vce Saturation (max): -
• Current Transfer Ratio (max): -

Switching Specifications
Propagation delay
time to logic low
at output
Propagation delay
time to logic high
at output
Common mode transient
immunity at logic high
level output
Common mode transient
immunity at logic low
level output
(*)JEDEC registered data.
(Note 1): Derate linearly above 50°C free−air temperature at a rate of 0.4mA / °C
(Note 2): Derate linearly above 50°C free−air temperature at a rate of 0.7mW / °C
(Note 3): Derate linearly above 25°C free−air temperature at a rate of 0.7mA / °C
(Note 4): Derate linearly above 25°C free−air temperature at a rate of 2.0mW / °C
(Note 5): DC CURRENT TRANSFER RATIO is defined as the ratio of output collector current, I
(Note 6): Pin 7 open.
(Note 7): Device considered a two−terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7 and 8
(Note 8): Use of a resistor between pin 5 and 7 will decrease gain and delay time.
(Note 9): Common mode transient immunity in logic high level is the maximum tolerable (positive) dv
Characteristic
(Note 6, 8)
(Note 6, 8)
LED input current, I
shorted together.
the leading edge of the common mode pulse, V
state (i.e., V
Common mode transient immunity in Logic Low level is the maximum tolerable (negative) dv
the trailing edge of the common mode pulse signal, V
low state (i.e., V
(Note 9)
(Note 9)
6N139
6N138
6N139
6N138
O
> 2.0V).
O
< 0.8V).
(Ta=25°C, V
F
Symbol
t
t
pHL
pLH
, times 100%.
CM
CM
(*)
(*)
H
L
Test
Circuit
1
1
2
2
CC
=5V, unless otherwise specified)
I
I
I
I
I
I
I
V
I
R
V
F
F
F
F
F
F
F
F
CM
L
CM
=0.5mA, R
=12mA, R
=1.6mA, R
=0.5mA, R
=12mA, R
=1.6mA, R
=0mA, R
=1.6mA
=2.2kΩ
4
=400V
=400V
CM
Test Condition
L
p−p
p−p
=2.2kΩ
L
L
, to assure that the output will remain in a logic high
L
L
L
L
=270Ω
=270Ω
=4.7kΩ
=2.2kΩ
=4.7kΩ
=2.2kΩ
CM
, to assure that the output will remain in a logic
Min.
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
−500
Typ.
500
0.2
5
1
5
1
4
6N138,6N139
O
Max.
, to the forward
25
10
60
35
⎯
⎯
1
7
2007-10-01
CM
CM
V / μs
V / μs
/ dt on
Unit
μs
μs
/ dt on