SDCFIF-001G-388 SanDisk, SDCFIF-001G-388 Datasheet - Page 45

• Manufacturer Part Number: SDCFIF-001G-388
• Description: COMPACT FLASH IND 1GB FIXED
• Manufacturer: SanDisk

Specifications of SDCFIF-001G-388

• Memory Size: 1GB
• Memory Type: CompactFLASH
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 585-1232; SDCFIF-001G-388

SanDisk Industrial Grade CompactFlash 5000
4.3
When CompactFlash Memory Card registers are accessed via memory
references, they appear in the common memory space window: 0-2K bytes as
shown in Table 33.
a.
b.
c.
© 2007 SanDisk® Corporation
Register 0 is accessed with -CE1 low and -CE2 low (and A0 = Do not care) as a
word register on the combined Odd Data Bus and Even Data Bus (D15-D0). This
register may also be accessed by a pair of byte accesses to the offset 0 with -CE1
low and -CE2 high. Note that the address space of this word register overlaps the
address space of the Error and Feature byte-wide registers that lie at offset 1.
When accessed twice as byte register with CE1 low, the first byte to be accessed
is the even byte of the word and the second byte accessed is the odd byte of the
equivalent word access. A byte access to register 0 with CE1 high and CE2 low
accesses the error (read) or feature (write) register.
Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at
offset 0 and 1.
Register 8 is equivalent to register 0, while register 9 accesses the odd byte.
Therefore, if the registers are byte accessed in the order 9 then 8 the data will be
transferred odd byte then even byte. Repeated byte accesses to register 8 or 0
will access consecutive (even then odd) bytes from the data buffer. Repeated
word accesses to register 8, 9 or 0 will access consecutive words from the data
buffer. Repeated byte accesses to register 9 are not supported. However,
repeated alternating byte accesses to registers 8 then 9 will access consecutive
(even then odd) bytes from the data buffer. Byte accesses to register 9 access
only the odd byte of the data.
Accesses to even addresses between 400h and 7FFh access register 8. Accesses
to
1 KByte memory window to the data register is provided to enable hosts to
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-REG
Memory Mapped Addressing
odd
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
A10
addresses
A9A4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
X
X
A3
between
Table 33: Memory Mapped Decoding
0
0
0
0
1
1
1
1
0
0
1
1
1
X
X
A2
0
0
1
1
0
0
1
1
0
0
0
1
1
X
X
A1
400h
38
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
A0
Offset
0
1
2
3
4
5
6
7
8
9
D
E
F
8
9
and
7FFh
Even RD Data a
Error Register b
Cylinder Low
Cylinder High
Select
Card/Head
Status
Dup Even RD
Data b
Dup Odd RD
Data b
Dup Error b
Alt Status
Drive Address
Sector Count
Sector No.
Even RD Data c
Odd RD Data c
-OE=0
access
Even WR Data a
Features b
Sector Count
Sector No.
Cylinder Low
Cylinder High
Select
Card/Head
Command
Dup Even WR
Data b
Dup Odd WR
Data b
Dup Features b
Device Ctl
Reserved
Even WR Data c
Even RD Data c
register
-WE=0
Product Manual
9.
July 2007
This