MT5VDDT1672AY-335K1 Micron Technology Inc, MT5VDDT1672AY-335K1 Datasheet - Page 6
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MT5VDDT1672AY-335K1
Manufacturer Part Number
MT5VDDT1672AY-335K1
Description
MODULE DDR 128MB 184-DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT5VDDT1672AY-335K1.pdf
(12 pages)
Specifications of MT5VDDT1672AY-335K1
Memory Type
DDR SDRAM
Memory Size
128MB
Speed
333MT/s
Package / Case
184-DIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184UDIMM
Device Core Size
72b
Organization
16Mx72
Total Density
128MByte
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.1A
Number Of Elements
5
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
General Description
Serial Presence-Detect Operation
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
The MT5VDDT872A, MT5VDDT1672A, and MT5VDDT3272A are high-speed CMOS,
dynamic random access 64MB, 128MB, and 256MB memory modules organized in a x72
configuration. These modules use DDR SDRAM devices with four internal banks.
DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for DDR SDRAM modules effectively consists of a single
2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands are registered at every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of DQS, as well as to both
edges of CK.
DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes are programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to V
module, permanently disabling hardware write protect.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2002 Micron Technology, Inc. All rights reserved.
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