MT9VDDF6472Y-335F1 Micron Technology Inc, MT9VDDF6472Y-335F1 Datasheet - Page 25

• Manufacturer Part Number: MT9VDDF6472Y-335F1
• Description: MODULE DDR SDRAM 512MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDF6472Y-335F1

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 167MHz
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.575A
• Number Of Elements: 9
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1293; MT9VDDF6472Y-335F1

Table 17: Register Timing Requirements and Switching Characteristics
Note: 1
NOTE:
pdf: 09005aef80e119b2, source: 09005aef807d56a1
DDF9C32_64x72G.fm - Rev. B 9/04 EN
REGISTER
or JESD82-4)
1. Timing and switching specifications for the register listed above are critical for proper operation of DDR SDRAM Regis-
2. Data inputs must be low a minimum time of t
3. Data and clock inputs must be held at valid levels (not floating) a minimum time of t
4. For data signal input slew rate
5. For data signal input slew rate
6. CK, CK# signals input slew rate
by JESD82-3
(bit pattern
tered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed
information for this register is available in JEDEC Standard JESD82.
LOW.
SSTL
SYMBOL
f
t
clock
t
t
t
inact
t
t
t
PHL
act
pd
su
w
h
Setup Time, Slow Slew Rate
Differential Inputs Inactive
Setup Time, Fast Slew Rate
Hold Time, Slow Slew Rate
Hold Time, Fast Slew Rate
Differential Inputs Active
Clock to Output Time
Reset to Output Time
Clock Frequency
PARAMERTER
Pulse Duration
1 V/ns.
0.5 V/ns and
1V/ns.
Time
Time
act
1V/ns.
max, after RESET# is taken HIGH.
30pF to GND and
CK, CK# HIGH or
HIGH, CK# LOW
HIGH, CK# LOW
Data Before CK
Data After CK
25
CONDITION
50 to V
LOW
256MB, 512MB (x72, ECC, SR)
TT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM RDIMM
V
0°C
DD
MIN
0.75
0.75
1.1
2.5
0.9
0.9
-
-
-
-
= +2.5V ±0.2V
T
A
inact
+70°C
MAX
max, after RESET# is taken
200
2.8
22
22
5
-
-
-
-
-
©2004 Micron Technology, Inc. All rights reserved.
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
4, 6
5, 6
4, 6
5, 6
2
3