MT16VDDF12864HY-335F2 Micron Technology Inc, MT16VDDF12864HY-335F2 Datasheet - Page 26
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MT16VDDF12864HY-335F2
Manufacturer Part Number
MT16VDDF12864HY-335F2
Description
MODULE DDR 1GB 200-SODIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT16VDDF12864HY-335F2.pdf
(30 pages)
Specifications of MT16VDDF12864HY-335F2
Memory Type
DDR SDRAM
Memory Size
1GB
Speed
167MHz
Package / Case
200-SODIMM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1292
MT16VDDF12864HY-335F2
MT16VDDF12864HY-335F2
Table 18: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
Table 19: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
NOTE:
pdf: 09005aef80a77a90, source: 09005aef80a646bc
DDF16C64_128x64HG.fm - Rev. D 9/04 EN
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
PARAMETER/CONDITION
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: I
INPUT LEAKAGE CURRENT: V
OUTPUT LEAKAGE CURRENT: V
STANDBY CURRENT: SCL = SDA = V
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
edge of SDA.
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
OUT
SS
SS
IN
; V
; V
= 3mA
= GND to V
OUT
DDSPD
DDSPD
DD
= GND to V
= +2.3V to +3.6V
- 0.3V; All other inputs = V
= +2.3V to +3.6V
t
WRC) is the time from a valid stop condition of a write sequence to the end of
DD
DD
26
DD
or V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SYMBOL
SS
t
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STA
SU:STO
t
t
t
t
HIGH
LOW
f
WRC
t
t
BUF
SCL
AA
DH
t
t
t
SYMBOL
F
R
I
V
DDSPD
V
V
V
I
I
I
I
LO
SB
CC
OL
LI
IH
IL
200-PIN DDR SODIMM
512MB, 1GB (x64, DR)
MIN
200
100
V
0.2
1.3
0.6
0.6
1.3
0.6
0.6
0
DD
MIN
2.3
-1
–
–
–
–
–
0.7
MAX
300
400
0.9
0.3
50
10
V
V
DD
DD
MAX
UNITS
3.6
0.4
10
10
30
KHz
2
ms
+ 0.5
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
©2004 Micron Technology, Inc.
0.3
NOTES
UNITS
mA
µA
µA
µA
1
2
2
3
4
V
V
V
V