MT18VDDF12872HY-335F1 Micron Technology Inc, MT18VDDF12872HY-335F1 Datasheet - Page 8

• Manufacturer Part Number: MT18VDDF12872HY-335F1
• Description: MODULE DDR SDRAM 1GB 200-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDF12872HY-335F1

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 333MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.53A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1173; MT18VDDF12872HY-335F1

I
Table 8:
PDF: 09005aef80e4880c/Source: 09005aef80e487d7
DDF18C128x72H.fm - Rev. B 10/07 EN
Parameter/Condition
Operating one bank active-precharge current: One device
bank; Active-precharge;
DM, and DQS inputs changing once per clock cycle; Address
and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: One
device bank; Active-read precharge; BL = 4;
t
changing once per clock cycle
Precharge power-down standby current: All device banks
idle; Power-down mode;
Idle standby current: CS# = HIGH; All device banks idle;
t
inputs changing once per clock cycle; V
and DM
Active power-down standby current: One device bank
active; Power-down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One
device bank; Active-precharge;
t
clock cycle; Address and other control inputs changing once
per clock cycle
Operating burst read current: BL = 2; Continuous burst
reads; One device bank active; Address and control inputs
changing once per clock cycle;
Operating burst write current: BL = 2; Continuous burst
writes; One device bank active; Address and control inputs
changing once per clock cycle;
DQS inputs changing twice per clock cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank
interleaving reads; (BL = 4) with auto precharge;
t
change only during active READ or WRITE commands
DD
CK =
CK =
CK =
RC =
t
Specifications
t
t
t
RC (MIN);
CK (MIN); I
CK (MIN); CKE = HIGH; Address and other control
CK (MIN); DQ, DM, and DQS inputs changing twice per
I
Values are shown for the
512Mb (64 Meg x 8) component data sheet
DD
t
CK =
OUT
Specifications and Conditions – 1GB
Notes:
= 0mA; Address and control inputs
t
CK (MIN); Address and control inputs
t
RC =
t
CK =
t
CK =
1. Value calculated as one module rank in this operating condition; all other module ranks are
2. Value calculated reflects all module ranks in this operating condition.
t
RC (MIN);
t
t
t
t
CK =
CK =
in I
CK (MIN); CKE = (LOW)
RC =
t
CK (MIN); CKE = LOW
DD
t
t
t
2P (CKE LOW) mode.
CK (MIN); I
CK (MIN); DQ, DM, and
RAS (MAX);
IN
MT46V64M8
t
CK =
= V
t
t
REF
t
REFC =
REFC = 7.8125µs
RC =
t
CK (MIN); DQ,
for DQ, DQS,
OUT
t
RC (MIN);
t
RFC (MIN)
= 0mA
DDR SDRAM only and are computed from values specified in the
1GB (x72, ECC, DR) 200-Pin DDR SDRAM SODIMM
8
Symbol
I
I
I
I
I
I
I
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
DD
4W
3N
5A
2P
3P
4R
2F
0
1
5
6
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
1
2
2
1
2
2
2
1
2
2
1
1,440
1,710
1,080
1,755
1,800
6,210
4,095
-40B
990
810
198
90
90
1,215
1,485
1,530
1,320
5,220
3,690
-335
810
630
900
180
90
90
©2004 Micron Technology, Inc. All rights reserved.
I
DD
-26A/
1,080
1,350
1,350
1,260
5,040
3,195
-265
720
540
810
180
Specifications
90
90
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA