MT9VDDF3272G-40BG3 Micron Technology Inc, MT9VDDF3272G-40BG3 Datasheet - Page 16
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MT9VDDF3272G-40BG3
Manufacturer Part Number
MT9VDDF3272G-40BG3
Description
MODULE DDR SDRAM 256MB 184-DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT9VDDF6472Y-40BF1.pdf
(30 pages)
Specifications of MT9VDDF3272G-40BG3
Memory Type
DDR SDRAM
Memory Size
256MB
Speed
200MHz
Package / Case
184-DIMM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1130
Table 14: Capacitance
Note: 11; notes appear on pages 18–20
Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC
Notes: 1–5, 8, 10, 12; notes appear on pages 18–20; 0°C
pdf: 09005aef80f6ab6a, source: 09005aef80f6ab23
DDAF9C32_64x72G.fm - Rev. C 9/04 EN
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PARAMETER
Input/Output Capacitance: DQ, DQS, DM
Input Capacitance: Command and Address, S#, CKE
Input Capacitance: CK, CK#
Operating Conditions
CL = 3
CL = 2.5
CL = 2
256MB, 512MB (x72, ECC, SR) PC3200
T
A
16
+70°C; V
SYMBOL
t
t
t
t
t
t
DQSCK
CK (2.5)
t
t
DD
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CK (2)
DQSQ
t
DQSH
DIPW
t
t
t
CK (3)
DQSL
DQSS
t
t
t
t
MRD
t
184-PIN DDR SDRAM RDIMM
t
t
QHS
t
t
DSH
t
t
t
t
RCD
t
IPW
RAS
RAP
t
t
DSS
t
t
t
RFC
QH
DH
AC
CH
HP
HZ
IH
IH
DS
RC
CL
LZ
IS
IS
= V
F
S
F
S
DD
SYMBOL
Q = +2.6V ±0.1V
t
CH,
C
C
C
-
-0.70
-0.60
-0.70
MIN
0.45
0.45
0.40
0.40
1.75
0.35
0.35
0.72
0.20
0.20
0.60
0.60
0.60
0.60
2.20
t
t
I0
I1
I2
5.0
6.0
7.5
QHS
10
40
15
55
70
15
HP
t
CL
-40B
70,000
MAX
+0.70
+0.60
+0.70
0.55
0.55
7.50
0.40
1.28
0.50
13
13
©2004 Micron Technology, Inc. All rights reserved.
MIN
2.5
4
–
UNITS
t
t
t
t
t
t
t
ns
CK
CK
ns
ns
ns
ns
ns
ns
ns
CK
CK
ns
CK
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX
3.5
5
4
NOTES
UNITS
40, 46
40, 46
40, 46
23, 27
23, 27
22, 23
16, 37
16, 37
22, 23
31,
26
26
27
30
12
12
12
12
44
pF
pF
pF