MT16HTF6464AY-667B4 Micron Technology Inc, MT16HTF6464AY-667B4 Datasheet - Page 4

• Manufacturer Part Number: MT16HTF6464AY-667B4
• Description: MODULE DDR2 SDRAM 512MB 240-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16HTF6464AY-667B4

• Memory Type: DDR2 SDRAM
• Memory Size: 512MB
• Speed: 333MHz
• Package / Case: 240-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1142

Table 5:
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
177, 179, 180, 182, 183, 188,
125, 134, 146, 155, 202, 211,
137, 138, 185, 186, 220, 221
57, 58, 60, 61, 63, 70, 176,
54 (2GB), 71, 190
196
Pin Numbers
73, 74, 192
223, 232
77, 195
52, 171
76, 193
(1GB, 2GB)
Pin Descriptions
Pin numbers may not correlate with symbols; refer to Table 4 on page 3 for more information
A0–A13
RAS#, CAS#, WE#
A0–A12
ODT0, ODT1
CKE0, CKE1
CK0, CK0#,
CK1, CK1#,
DM0–DM7
CK2, CK2#
BA2
BA0, BA1,
Symbol
S0#, S1#
(1GB, 2GB)
(2GB)
(512MB)
512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Input
Input
Input
Input
Input
Input
Input
Input
Type
On-die termination: ODT (registered HIGH) enables termination
resistance internal to the DDR2 SDRAM. When enabled, ODT is
only applied to each of the following pins: DQ, DQS, DQS#, and
DM. The ODT input will be ignored if disabled via the LOAD
MODE command.
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE
(registered LOW) deactivates clocking circuitry on the DDR2
SDRAM. The specific circuitry that is enabled/disabled is
dependent on the DDR2 SDRAM configuration and operating
mode. CKE LOW provides precharge power-down and SELF
REFRESH operations (all device banks idle), or ACTIVE power-
down (row ACTIVE in any device bank). CKE is synchronous for
power-down entry, power-down exit, output disable, and for
SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit.
Input buffers (excluding CK, CK#, CKE, and ODT) are disabled
during power-down. Input buffers (excluding CKE) are disabled
during SELF REFRESH. CKE is an SSTL_18 input but will detect a
LVCMOS LOW level when V
After V
initialization sequence, it must be maintained for proper
operation of the CKE receiver. For proper SELF REFRESH
operation, V
Chip select: S# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when
S# is registered HIGH. S# provides for external rank selection on
systems with multiple ranks. S# is considered part of the
command code.
Command inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Bank address inputs: BA0–BA1/BA2 define to which device bank
an ACTIVE, READ, WRITE, or PRECHARGE command is being
applied. BA0–BA1/BA2 define which mode register including
MR, EMR, EMR(2), and EMR(3) is loaded during the LMR
command.
Address inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory
array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the precharge applies to one
device bank (A10 LOW, device bank selected by BA0–BA1/BA2)
or all device banks (A10 HIGH). The address inputs also provide
the op-code during a LMR command.
Input data mask: DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH along with that
input data during a WRITE access. DM is sampled on both edges
of DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.
4
REF
has become stable during the power on and
Micron Technology, Inc., reserves the right to change products or specifications without notice.
REF
must be maintained to this input.
Pin Assignments and Descriptions
Description
DD
is applied during first power-up.
©2003 Micron Technology, Inc. All rights reserved.