MT9VDDT6472AG-335F1 Micron Technology Inc, MT9VDDT6472AG-335F1 Datasheet - Page 11

• Manufacturer Part Number: MT9VDDT6472AG-335F1
• Description: MODULE DDR SDRAM 512MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDT6472AG-335F1

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Commands
Operation Truth Table, provide a general reference of
available commands. For a more detailed description
Table 8:
DESELECT and NOP are functionally interchangeable; all states and sequences not shown are illegal or reserved
NOTE:
Table 9:
Used to mask write data; provided coincident with the corresponding data
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A11 (128MB) or A0–A12 (256MB, 512MB) provide device row address.
3. BA0–BA1 provide device bank address; A0–A9 (128MB, 256MB) or A0–A9, A11 (512MB) provide device column address;
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0–
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls device row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 =
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
WRITE Enable
WRITE Inhibit
Table 8, Commands Truth Table, and Table 9, DM
A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
bursts with auto precharge enabled and for write bursts.
BA1 are “Don’t Care.”
1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (128MB) or A0–A12
(256MB, 512MB) provide the op-code to be written to the selected mode register.
Commands Truth Table
DM Operation Truth Table
NAME (FUNCTION)
NAME (FUNCTION)
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
11
of commands and operations, refer to the 128Mb,
256Mb, or 512Mb DDR SDRAM component data
sheets.
CS#
H
Micron Technology, Inc., reserves the right to change products or specifications without notice.
L
L
L
L
L
L
L
L
184-Pin DDR SDRAM UDIMM
RAS# CAS#
H
H
H
H
X
L
L
L
L
H
H
H
H
X
L
L
L
L
WE#
DM
X
H
H
H
H
L
L
L
L
H
L
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
©2004 Micron Technology, Inc.
NOTES
Valid
DQS
6, 7
X
1
1
2
3
3
4
5
8