MT18HTF12872Y-53ED2 Micron Technology Inc, MT18HTF12872Y-53ED2 Datasheet
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MT18HTF12872Y-53ED2
Specifications of MT18HTF12872Y-53ED2
Related parts for MT18HTF12872Y-53ED2
MT18HTF12872Y-53ED2 Summary of contents
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DDR2 SDRAM Registered DIMM (RDIMM) MT18HTF6472 – 512MB MT18HTF12872(P) – 1GB MT18HTF25672(P) – 2GB For component data sheets, refer to Micron's Web site: Features • 240-pin, registered dual in-line memory module • Fast data transfer rates: PC2-3200, PC2-4200, PC2- 5300, ...
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... Part Numbers and Timing Parameters – 1GB Modules Base device: MT47H128M4, 2 Part Number Module Density MT18HTF12872(P)Y-80E__ MT18HTF12872(P)Y-800__ MT18HTF12872(P)Y-667__ MT18HTF12872(P)Y-53E__ MT18HTF12872(P)Y-40E__ Table 5: Part Numbers and Timing Paramters – 2GB Modules Base device: MT47H256M4, 2 Part Number Module Density MT18HTF25672(P)Y-80E__ MT18HTF25672(P)Y-800__ MT18HTF25672(P)Y-667__ MT18HTF25672(P)Y-53E__ MT18HTF25672(P)Y-40E__ Notes: 1. Data sheets for the base devices can be found on Micron’ ...
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Pin Assignments and Descriptions Table 6: Pin Assignments 240-Pin RDIMM Front Pin Symbol Pin Symbol Pin DQ19 61 REF DQ0 33 DQ24 63 4 DQ1 34 DQ25 64 5 ...
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Table 7: Pin Descriptions Symbol Type ODT0 Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the (SSTL_18) DDR2 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, DQS#, and CB. The ODT input ...
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Functional Block Diagram Figure 2: Functional Block Diagram V SS RS0# DQS2 DQS2# DQS3 DQS3# U6, U17 S0# RS0#: DDR2 SDRAM e BA0–BA1/BA2 RBA0 – RBA1/RBA2: DDR2 SDRAM g A0–A12/A13 RA0–RA12/RA13: ...
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... READs and by the memory controller during WRITEs. DQS is edge- aligned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. ...
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... Simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. JEDEC modules are currently designed using simulations to close timing budgets. Component AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron’ ...
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I Specifications DD Table 10: DDR2 I Specifications and Conditions – 512MB DD Values shown for MT47H64M4 DDR2 SDRAM only and are computed from values specified in the 256Mb (64 Meg x 4) component data sheet Parameter/Condition Operating one bank ...
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Table 11: DDR2 I Specifications and Conditions – 1GB DD Values shown for MT47H128M4 DDR2 SDRAM only and are computed from values specified in the 512Mb (128 Meg x 4) component data sheet Parameter/Condition Operating one bank active-precharge current: t ...
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Table 12: DDR2 I Specifications and Conditions (Die Revision A) – 2GB DD Values shown for MT47H256M4 DDR2 SDRAM only and are computed from values specified in the 1Gb (256 Meg x 4) component data sheet Parameter/Condition Operating one bank ...
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Table 13: DDR2 I Specifications and Conditions (Die Revision E) – 2GB DD Values shown for MT47H256M4 DDR2 SDRAM only and are computed from values specified in the 1Gb (256 Meg x 4) component data sheet Parameter/Condition Operating one bank ...
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Register and PLL Specifications Table 14: Register Specifications SSTU32866 devices or equivalent JESD82-16 Parameter Symbol DC high-level input voltage DC low-level input voltage high-level IH AC ...
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Table 15: PLL Specifications CU877 device or equivalent JESD82-8.01 Parameter Symbol DC high-level input voltage V DC low-level input voltage V V Input voltage (limits high-level input voltage DC low-level input voltage V Input differential-pair cross V voltage ...
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Serial Presence-Detect Table 17: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage 3mA OUT Input ...
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Table 19: Serial Presence-Detect Matrix Byte Description 0 Number of SPD bytes used by Micron 1 Total number of bytes in SPD device 2 Fundamental memory type 3 Number of row addresses on SDRAM 4 Number of column addresses on ...
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Table 19: Serial Presence-Detect Matrix (continued) Byte Description 27 MIN row precharge time, 28 MIN row active-to-row active, 29 MIN RAS#-to-CAS# delay, 30 MIN active-to-precharge, 31 Module rank density 32 Address and command setup time, 33 Address and command hold ...
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Table 19: Serial Presence-Detect Matrix (continued) Byte Description 47–61 Optional features, not supported 62 SPD revision 63 Checksum for bytes 0–62 ECC/ECC and parity 64 Manufacturer’s JEDEC ID code 65–71 Manufacturer’s JEDEC ID code 72 Manufacturing location 73–90 Module part ...
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Module Dimensions Figure 3: 240-Pin DDR2 RDIMM 2.00 (0.079) R (4X 2.50 (0.098) D (2X) 2.30 (0.091) TYP PIN 1 1.0 (0.039) TYP U13 U14 PIN 240 55.0 (2.165) TYP Notes: 1. All dimensions are in millimeters (inches); ...