MT18HTF25672AY-53EA1 Micron Technology Inc, MT18HTF25672AY-53EA1 Datasheet - Page 15

• Manufacturer Part Number: MT18HTF25672AY-53EA1
• Description: MODULE SDRAM DDR2 2GB 240DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18HTF25672AY-53EA1

• Memory Type: DDR2 SDRAM
• Memory Size: 2GB
• Speed: 533MT/s
• Package / Case: 240-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 13: DDR2 I
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
PDF: 09005aef80e8ad4d
htf18c64_128_256_512x72ay – Rev. I 3/10 EN
Parameter
Operating one bank active-precharge current:
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
4, CL = CL (I
(I
Address bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
Active power-down current: All device banks open;
=
puts are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
(I
Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
read, I
MAX (I
mands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:
(I
trol and address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
RC (I
RAS MAX (I
DD
DD
DD
t
CK (I
),
),
) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
DD
t
t
RCD =
RP =
OUT
DD
DD
),
),
t
); CKE is LOW; Other control and address bus in-
RAS =
= 0mA; BL = 4, CL = CL (I
t
t
DD
RP (I
RP =
DD
t
RCD (I
), AL = 0;
),
t
DD
t
t
RP =
RAS MIN (I
RP (I
); CKE is HIGH, S# is HIGH between valid commands;
DD
DD
DD
); CKE is HIGH, S# is HIGH between valid commands;
t
RP (I
Specifications and Conditions (Die Revision A) – 2GB
t
CK =
t
); CKE is HIGH, S# is HIGH between valid com-
CK =
DD
DD
t
); CKE is HIGH, S# is HIGH between valid com-
DD
CK (I
t
); CKE is HIGH, S# is HIGH between valid
CK (I
512MB, 1GB, 2GB, 4GB (x72, DR) 240-Pin DDR2 SDRAM UDIMM
), AL = 0;
DD
DD
DD
),
), AL = 0;
); REFRESH command at every
t
RC =
t
CK =
t
RC (I
t
CK =
t
CK (I
DD
t
CK =
t
CK =
),
t
t
DD
CK (I
CK =
t
RAS =
),
t
CK
t
CK (I
t
t
RAS =
DD
CK (I
t
OUT
CK =
t
DD4W
t
CK (I
CK =
),
15
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
DD
RAS MIN
t
= 0mA; BL =
DD
RAS =
),
t
DD
t
CK (I
RAS MAX
),
t
t
CK (I
); CKE is
RAS =
t
RC =
t
RFC
t
DD
RAS
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
);
);
Symbol
I
I
I
I
I
I
I
DD4W
I
I
DD2Q
I
I
DD2N
DD3N
DD4R
DD2P
DD3P
DD0
DD1
DD5
DD6
1
1
2
2
2
2
1
2
2
2
1
-80E/
1053
1170
1260
1350
1728
1773
5040
-800
963
126
810
252
126
1080
1260
1503
1503
4680
-667
873
963
126
990
720
252
126
© 2003 Micron Technology, Inc. All rights reserved.
I
DD
1233
1368
4500
-53E
Specifications
783
918
126
738
810
630
252
990
126
-40E
1053
1053
3960
693
873
126
630
720
630
252
810
126
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA