MT18HTF6472Y-40EB2 Micron Technology Inc, MT18HTF6472Y-40EB2 Datasheet - Page 8
![MODULE SDRAM DDR2 512MB 240DIMM](/photos/7/83/78383/mfg557-240-dimm_sml.jpg)
MT18HTF6472Y-40EB2
Manufacturer Part Number
MT18HTF6472Y-40EB2
Description
MODULE SDRAM DDR2 512MB 240DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT18HTF25672PY-667A1.pdf
(18 pages)
Specifications of MT18HTF6472Y-40EB2
Memory Type
DDR2 SDRAM
Memory Size
512MB
Speed
400MT/s
Package / Case
240-DIMM
Main Category
DRAM Module
Sub-category
DDR2 SDRAM
Module Type
240RDIMM
Device Core Size
72b
Organization
64Mx72
Total Density
512MByte
Chip Density
256Mb
Access Time (max)
60ps
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
1.8V
Operating Current
2.25A
Number Of Elements
18
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
240
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
I
Table 10:
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL = CL (I
t
bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current: All device banks idle;
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
Active power-down current: All device banks open;
t
inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
commands; Other control and address bus inputs are switching; Data bus inputs
are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
reads; I
(I
bus inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; I
t
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
DD
RC =
RCD =
CK =
RAS =
RP =
CK =
DD
),
Specifications
t
t
t
t
t
RP (I
RC (I
RP =
CK (I
CK (I
t
OUT
OUT
t
RAS MAX (I
RCD (I
DD
DD
DD
= 0mA; BL = 4, CL = CL (I
DD
t
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
RP (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus
),
DDR2 I
Values shown for MT47H64M4 DDR2 SDRAM only and are computed from values specified in the
256Mb (64 Meg x 4) component data sheet
); CKE is LOW; Other control and address bus
),
DD
t
t
RAS =
DD
RC =
); CKE is HIGH, S# is HIGH between valid commands; Address
); CKE is HIGH, S# is HIGH between valid commands; Address
DD
t
t
),
CK =
DD
RC (I
t
RAS MIN (I
t
DD
RP =
t
CK =
Specifications and Conditions – 512MB
), AL = 0;
DD
t
CK (I
),
t
RP (I
t
CK (I
t
RRD =
DD
DD
DD
DD
),
512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
DD
DD
t
); CKE is HIGH, S# is HIGH between valid
CK =
t
); CKE is HIGH, S# is HIGH between valid
), AL = 0;
RC =
); REFRESH command at every
), AL =
t
RRD (I
t
CK (I
t
RC (I
t
DD
RCD (I
t
DD
CK =
),
DD
),
t
t
DD
RCD =
),
CK =
t
t
DD
RAS =
t
t
CK =
t
4W
RAS =
CK (I
CK =
) - 1 x
t
CK (I
t
t
DD
t
RCD (I
OUT
CK =
CK (I
t
t
t
CK (I
RAS MAX (I
t
CK =
RAS MIN (I
),
t
8
DD
CK (I
t
= 0mA; BL = 4,
RAS =
DD
t
DD
),
DD
CK (I
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
),
CK (I
DD
); CKE is
); CKE is
);
DD
t
t
RFC (I
RAS MAX
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
DD
); CKE is
); CKE
),
),
DD
)
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
6
7
1,440
1,620
2,880
2,700
3,060
4,320
-53E
630
630
450
108
720
©2003 Micron Technology, Inc. All rights reserved.
90
90
I
DD
Specifications
1,350
1,530
2,250
2,070
2,970
4,140
-40E
450
540
360
108
540
90
90
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA