MT18LSDT12872AG-13EC1 Micron Technology Inc, MT18LSDT12872AG-13EC1 Datasheet
MT18LSDT12872AG-13EC1
Specifications of MT18LSDT12872AG-13EC1
Related parts for MT18LSDT12872AG-13EC1
MT18LSDT12872AG-13EC1 Summary of contents
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... Column Addressing Module Ranks PDF: 09005aef8088b1bf/Source: 09005aef808807ca SD9_18C64_128X72AG.fm - Rev. C 6/05 EN Products and specifications discussed herein are subject to change by Micron without notice. 512MB (SR), 1GB (DR): (x72, ECC) 168-Pin SDRAM UDIMM www.micron.com/products/modules. Figure 1: Standard 1.375in./34.93mm Low Profile 1.125in./28.58mm Options • Package 168-pin DIMM (standard) 168-pin DIMM (lead-free) • ...
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... MT9LSDT6472AG-133_ MT9LSDT6472AG-133_ MT18LSDT12872AG-13E_ MT18LSDT12872AG-13E_ MT18LSDT12872AG-133_ MT18LSDT12872AG-133_ Notes: 1. The designators for component and PCB revision are the last two characters of each part number Consult factory for current revision codes. Example: MT9LSDT6472AG-133B1. PDF: 09005aef8088b1bf/Source: 09005aef808807ca SD9_18C64_128X72AG.fm - Rev. C 6/05 EN 512MB (SR), 1GB (DR): (x72, ECC) 168-Pin SDRAM UDIMM ...
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Pin Assignments and Descriptions Table 4: Pin Assignment 168-Pin DIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol CB1 DQ0 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to the Table 4 on page 3 for pin number and symbol information Pin Numbers 27, 111, 115 42, 79, 125, 163 63, 128 30, 45,114, 129 28, ...
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... V Supply Power Supply: +3.3V ±0.3V Supply Ground – Not Connected: These pins are not connected on these modules. Micron Technology, Inc., reserves the right to change products or specifications without notice. 5 Pin Assignments and Descriptions ©2002 Micron Technology, Inc. All rights reserved. ...
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... Functional Block Diagrams All resistor values are 10Ω unless otherwise specified. Per industry standard, Micron modules use various component speed grades as referenced in the module part numbering guide at numbering.html. Standard modules use the following SDRAM devices: MT48LC64M8A2TG. Lead-free modules use the following SDRAM devices: MT48LC64M8A2P . ...
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Figure 4: Dual Rank S0# DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 S2# DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 ...
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... READ or WRITE command are used to select the starting column location for the burst access. These modules provide for programmable READ or WRITE burst lengths locations, or the full page, with a burst terminate option. An AUTO PRECHARGE func- tion may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence ...
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INHIBIT or NOP . Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100µs delay has been satisfied with at least ...
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Figure 5: Mode Register Definition Diagram M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices. PDF: 09005aef8088b1bf/Source: 09005aef808807ca SD9_18C64_128X72AG.fm - Rev. C 6/05 EN 512MB (SR), 1GB (DR): (x72, ECC) 168-Pin SDRAM UDIMM A12 A11 A10 ...
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Table 6: Burst Definition Table Burst Length Full Page (y) Notes: 1. For full-page accesses 2,048. 2. For the block. 3. For within the block. 4. For ...
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Figure 6: CAS Latency Diagram COMMAND COMMAND CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ com- mand and the availability of the first piece of output data. The latency can be ...
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Write Burst Mode When the burst length programmed via M0–M 2 applies to both READ and WRITE bursts; when the programmed burst length applies to READ bursts, but write accesses are single-location (non burst) ...
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Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections ...
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Table 11: DC Electrical Characteristics and Operating Conditions – 1GB (continued) Notes notes appear on page 19; V Parameter/Condition Output leakage current: DQ pins are disabled; 0V ≤ V ≤ OUT DD Output levels: Output ...
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Capacitance Table 14: Capacitance – 128MB Note 2; notes appear on page 19 Parameter Input capacitance: Address and command Input capacitance: CK0 Input capacitance: CK2 Input capacitance: S0# Input capacitance: S2# Input capacitance: CKE Input capacitance: DQMB0, 2– ...
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AC Operating Specifications Table 16: Electrical Characteristics and Recommended AC Operating Conditions Notes 11, 31; notes appear on page 19 Module AC timing parameters comply with PC100 and PC133 design specifications, based on component parameters AC ...
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Table 17 Functional Characteristics Notes 11, 31; notes appear on page 19 Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit ...
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Notes 1. All voltages referenced This parameter is sampled. V 1.4V MHz with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications ...
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... ECC) 168-Pin SDRAM UDIMM t WR, and PRECHARGE commands). CKE may 7.5ns; for -133 and t RAS used in -13E speed grade modules is calculated from Micron Technology, Inc., reserves the right to change products or specifications without notice. 20 Notes t RP) begins at 7ns for -13E; ...
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Serial Presence Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 7, and ...
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Figure 8: Definition of Start and Stop SCL SDA Figure 9: Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver Table 18: EEPROM Device Select Code The most significant bit (b7) is sent first ...
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Figure 10: SPD EEPROM Timing Diagram SCL t SU:STA SDA IN SDA OUT Table 20: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic ...
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Table 21: Serial Presence-Detect EEPROM AC Operating Conditions (continued) All voltages referenced to V Parameter/Condition Stop condition setup time WRITE cycle time Notes avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 ...
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Table 22: Serial Presence-Detect Matrix V = +3.3V ±0.3V; “1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW” DD Byte Description 0 Number of bytes used by Micron 1 Total number of SPD memory bytes 2 Memory type 3 Number of ...
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... Entry (Version) t 60ns (-13E) RC 66ns (-133) Rev. 2.0 (-13E) (-133) MICRON 1– 12 1–9 0 100 MHz (-13E/-133) t RAS used for -13E modules is calculated from Micron Technology, Inc., reserves the right to change products or specifications without notice. 26 Serial Presence Detect MT9LSDT6472A MT18LSDT12872A ...
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Module Dimensions Figure 11: 168-Pin DIMM Dimensions – 512MB U2 U1 0.079 (2.00) R (2X) 0.118 (3.00) (2X) 0.118 (3.00) TYP 0.250 (6.35) TYP 0.118 (3.00) TYP 2.625 (66.68) PIN 1 (PIN 85 ON BACKSIDE) 0.079 (2.00) R (2X) U1 ...
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Figure 12: 168-Pin DIMM Dimensions – 1GBs U1 U2 0.079 (2.00) R (2X) 0.118 (3.00) (2X) 0.118 (3.00) TYP 0.118 (3.00) TYP 2.625 (66.68) PIN 1 U11 U12 PIN 168 0.079 (2.00) R (2X 0.118 (3.00) (2X) 0.118 ...
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