MT36VDDF12872G-265G3 Micron Technology Inc, MT36VDDF12872G-265G3 Datasheet
MT36VDDF12872G-265G3
Specifications of MT36VDDF12872G-265G3
Related parts for MT36VDDF12872G-265G3
MT36VDDF12872G-265G3 Summary of contents
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... PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. MT36VDDF12872 – 1GB MT36VDDF25672 – 2GB For the latest data sheet, please refer to the Micron site: www.micron.com/products/modules Figure 1: 184-Pin DIMM (MO-206) Standard 1.7in. (43.18mm) Low-Profile (1GB) 1.2in. (30.48mm) Low Profile (2GB) 1.2in. (30.48mm) OPTIONS • ...
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... MT36VDDF25672Y-26A__ MT36VDDF25672G-265__ MT36VDDF25672Y-265__ MT36VDDF25672G-202__ MT36VDDF25672Y-202__ NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT36VDDF12872G-265B1. pdf: 09005aef80772fd2, source: 09005aef8075ebf6 DDF36C128_256x72G.fm - Rev. D 9/04 EN CONFIGURATION MODULE BANDWIDTH 1GB 128 Meg x 72 ...
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Table 3: Pin Assignment (184-Pin DIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL DQ17 47 REF 2 DQ0 25 DQS2 DQ1 DQS0 ...
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Table 5: Pin Assignment (184-Pin DIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL DQ17 47 REF 2 DQ0 25 DQS2 DQ1 DQS0 ...
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Table 7: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL 10 63, 65, 154 WE#, CAS#, RAS# 137, 138 CK0, CK0# 21, 111 CKE0, CKE1 ...
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... Supply Ground. SS Supply Serial EEPROM positive power supply: +2.3V to +3.6V. DDSPD DNU — Do Not Use: Thes pins are not connected on these modules, but are assigned pins on other modules in this product family NC — No Connect: These pins should be left unconnected. 6 1GB, 2GB (x72, ECC, DR) ...
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... SA1 SA2 Standard modules use the following DDR SDRAM devices: MT46V64M4FN (1GB); MT46V128M4FN (2GB) Lead-free modules use the following DDR SDRAM devices: MT46V64M4BN (1GB); MT46V128M4BN (2GB) Micron Technology, Inc., reserves the right to change products or specifications without notice. 7 1GB, 2GB (x72, ECC, DR) ...
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... SA1 SA2 Standard modules use the following DDR SDRAM devices: MT46V64M4FN (1GB); MT46V128M4FN (2GB) Lead-free modules use the following DDR SDRAM devices: MT46V64M4BN (1GB); MT46V128M4BN (2GB) Micron Technology, Inc., reserves the right to change products or specifications without notice. 8 1GB, 2GB (x72, ECC, DR) ...
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... SPD SDA SA0 SA1 SA2 Standard modules use the following DDR SDRAM devices: MT46V64M4FN (1GB); MT46V128M4FN (2GB) Lead-free modules use the following DDR SDRAM devices: MT46V64M4BN (1GB); MT46V128M4BN (2GB) 9 1GB, 2GB (x72, ECC, DR) 184-PIN DDR RDIMM DQS4 DQS CS# DQS CS# DQ DQ32 ...
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... DDR SDRAM modules use internally configured quad- bank DDR SDRAM devices. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation. Double data rate architecture is essentially a 2n-prefetch architec- ture with an interface designed to transfer two data words per clock cycle at the I/O pins ...
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Vio- lating either of these requirements will result in unspecified operation. Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequential ...
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Table 8: Burst Definition Table ORDER OF ACCESSES WITHIN A BURST STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1-2 ...
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All other combinations of values for A7–A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future ver- sions may result. Extended Mode Register The extended ...
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Commands Table Table 10:, Commands Truth Table, and Table Table 11:, DM Operation Truth Table, provide a general reference of available commands. For a more detailed Table 10: Commands Truth Table CKE is HIGH for all commands shown except SELF ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 14: I Specifications and Conditions – 1GB DD DDR SDRAM components only Notes: 1–5, 14, 48; notes appear following parameter tables; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN ...
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Table 15: I Specifications and Conditions – 2GB DD DDR SDRAM components only Notes: 1–5, 14, 48; notes appear following parameter tables; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN ...
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Table 16: Capacitance Note: 11; notes appear following parameter tables PARAMETER Input/Output Capacitance: DQ, DQS Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK, CK# Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-335 and ...
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Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-335 and -262 Speed Grades) (Continued) Notes: 1–5, 14; notes appear following parameter tables; 0°C AC CHARACTERISTICS PARAMETER DQS read preamble DQS read postamble ACTIVE bank a to ...
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Table 18: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, and -202 Speed Grades) (Continued) Notes: 1–5, 14; notes appear following parameter tables; 0°C AC CHARACTERISTICS PARAMETER Address and control input setup time (fast slew rate) ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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REFRESH command must be asserted at least once every 70.3µs; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving t t other specifications: HP ...
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HP min is the lesser of CL minimum and minimum actually applied to the device CK and CK# inputs, collectively during bank active. 31. READs and WRITEs with auto precharge are not t allowed to be issued ...
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The current Micron part operates below the slow- est JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 41. For -335, -262, -26A, and -265 35mA per DDR SDRAM device ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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Table 19: Register Timing Requirements and Switching Characteristics Note 1 REGISTER SYMBOL PARAMERTER f Clock Frequency clock t Clock to Output Time pd t Reset To Output Time PHL SSTL t Pulse Duration w (bit pattern by JESD82-3 t Differential ...
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Table 20: PLL Clock Driver Timing Requirements and Switching Characteristics Note 1 PARAMETER SYMBOL Operating Clock Frequency Input Duty Cycle Stabilization Time Cycle to Cycle Jitter Static Phase Offset Output Clock Skew Period Jitter Half-Period Jitter t Input Clock Slew ...
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... NOTE: 1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM) across all modules. 2. The component case temperature measurements shown above were obtained experimentally. The typical system to be used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered memory modules ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Fig- ure 15, Data Validity, and Figure 16, Definition ...
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Table 21: EEPROM Device Select Code The most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 22: EEPROM Operating Modes MODE Current Address Read Random Address Read Sequential Read ...
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Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION Supply Voltage Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs Output Low Voltage 3mA OUT Input ...
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Table 24: Serial Presence-Detect Matrix 0 “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE DESCRIPTION 0 Number of SPD Bytes Used by Micrpn 1 Tptal Number pf Bytes in SPD Device 2 Fundamental Mempry Type 3 Number of Row ...
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Table 24: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE DESCRIPTION 30 Minimum RAS# Pulse Width, (See note 2) 31 Module Rank Density 32 Address and Command Setup Time, (See note 3) 33 Address and Command ...
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... The value of RAS used for -262/-26A/-265 modules is calculated from 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is repesented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini- mum slew rate is met ...
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Figure 19: Standard 184-Pin DDR DIMM Dimensions 0.079 (2.00) R (4X) U11 U12 U13 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.050 (1.27) TYP. 0.091 (2.30) 2.55 (64.77) TYP. U19 U20 U29 U30 PIN 184 ...
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Figure 20: Low-Profile (1GB) 184-Pin DDR DIMM Dimensions 0.079 (2.00 (4X) U13 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.050 (1.27) 0.091 (2.30) TYP. U21 U22 U23 U34 PIN 184 Figure 21: Low-Profile (2GB) ...
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Data Sheet Designation Released (No Mark): This data sheet contains mini- mum and maximum limits specified over the complete power supply and temperature range for production 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, ...