MT5LSDT472AG-133G6 Micron Technology Inc, MT5LSDT472AG-133G6 Datasheet - Page 17
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MT5LSDT472AG-133G6
Manufacturer Part Number
MT5LSDT472AG-133G6
Description
MODULE SDRAM 32MB 168DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT5LSDT1672AG-133D1.pdf
(22 pages)
Specifications of MT5LSDT472AG-133G6
Memory Type
SDRAM
Memory Size
32MB
Speed
133MHz
Package / Case
168-DIMM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
SPD Clock and Data Conventions
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions, as
indicated in Figure 6, Data Validity, and Figure 7, Defi-
nition of Start and Stop.
SPD Start Condition
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
SPD Stop Condition
tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.
32, 64, 128MB x 64 SDRAM DIMM
SD5C4_8_16x72AG.fm - Rev. C 6/04 EN
SDA
SCL
Data states on the SDA line can change only during
All commands are preceded by the start condition,
All communications are terminated by a stop condi-
SCL from Master
Data Output
from Transmitter
Data Output
from Receiver
Figure 6: Data Validity
DATA STABLE
Figure 8: Acknowledge Response from Receiver
DATA
CHANGE
DATA STABLE
17
SPD Acknowledge
cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data as indicated in
Figure 8, Acknowledge Response from Receiver, on
page 17.
acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode, the SPD device
will transmit eight bits of data, release the SDA line,
and monitor the line for an acknowledge. If an
acknowledge is detected and no stop condition is gen-
erated by the master, the slave will continue to trans-
mit data. If an acknowledge is not detected, the slave
will terminate further data transmissions and await
the stop condition to return to standby power mode.
SDA
Figure 7: Definition of Start and Stop
SCL
Acknowledge is a software convention used to indi-
The SPD device will always respond with an
32MB, 64MB, 128MB (x72, SR)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
START
BIT
168-PIN SDRAM UDIMM
8
©2004 Micron Technology, Inc. All rights reserved.
Acknowledge
9
STOP
BIT