MT5VDDT872AG-265B1 Micron Technology Inc, MT5VDDT872AG-265B1 Datasheet - Page 10
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MT5VDDT872AG-265B1
Manufacturer Part Number
MT5VDDT872AG-265B1
Description
MODULE SDRAM DDR 64MB 184DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT5VDDT1672AY-335K1.pdf
(12 pages)
Specifications of MT5VDDT872AG-265B1
Memory Type
DDR SDRAM
Memory Size
64MB
Speed
266MT/s
Package / Case
184-DIMM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 12:
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Power-
down mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock
cycle; V
Active power-down standby current: One device bank active; Power-
down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active;
changing twice per clock cycle; Address and other control inputs changing
once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock
cycle;
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving
reads; BL = 4 with auto precharge;
Address and control inputs change only during active READ or WRITE
commands
CK =
RC =
t
t
t
t
RC (MIN);
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
CK =
CK =
t
IN
RC =
= V
t
t
REF
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
t
t
t
RAS (MAX);
I
Values are shown for the MT46V32M16 DDR SDRAM only and are computed from values specified in the
512Mb (32 Meg x 16) component data sheet
CK =
CK =
DD
for DQ, DQS, and DM
t
CK =
Specifications and Conditions – 256MB
t
t
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
t
CK (MIN); I
OUT
t
CK =
= 0mA
t
CK (MIN); DQ, DM, and DQS inputs
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
OUT
t
RC =
= 0mA; Address and control inputs
t
RC (MIN);
t
t
RC =
CK =
t
t
REFC =
REFC = 7.8125µs
t
t
t
RC (MIN);
CK (MIN);
CK =
10
t
RFC (MIN)
t
CK (MIN);
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
I
I
I
I
I
I
I
DD
DD
DD
I
I
DD
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
3N
5A
2P
2F
3P
4R
0
1
5
6
7
1,050
1,075
1,725
2,400
-40B
775
975
275
225
300
25
55
30
Electrical Specifications
©2002 Micron Technology, Inc. All rights reserved.
1,450
2,025
-335
650
800
225
175
250
825
975
25
50
25
1,400
1,750
-265
575
725
200
150
225
725
675
25
50
25
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA