MT8HTF3264HY-667B3 Micron Technology Inc, MT8HTF3264HY-667B3 Datasheet - Page 6

• Manufacturer Part Number: MT8HTF3264HY-667B3
• Description: MODULE DDR2 256MB 200SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8HTF3264HY-667B3

• Memory Type: DDR2 SDRAM
• Memory Size: 256MB
• Speed: 667MT/s
• Package / Case: 200-SODIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Description
Serial Presence-Detect Operation
PDF: 09005aef80eec96e/Source: 09005aef80eec946
HTF8C32_64_128x64HG.fm - Rev. E 6/08 EN
The MT8HTF3264H, MT8HTF6464H, and MT8HTF12864H DDR2 SDRAM modules are
high-speed, CMOS, dynamic random-access 256MB, 512MB, and 1GB memory modules
organized in x64 configuration. DDR2 SDRAM modules use internally configured quad-
bank (256Mb, 512Mb) or eight-bank (1Gb) DDR2 SDRAM devices.
DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 4n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-
wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding
n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
device during reads and by the memory controller during writes. DQS is edge-aligned
with data for reads and center-aligned with data for writes.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module
type and various SDRAM organizations and timing parameters. The remaining 128 bytes
of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I
which provide fourt unique DIMM/EEPROM addresses. Write protect (WP) is connected
to V
2
C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[1:0],
SS
, permanently disabling hardware write protect.
256MB, 512MB, 1GB: (x64, SR) 200-Pin DDR2 SDRAM SODIMM
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2004 Micron Technology, Inc. All rights reserved.