MT8VDDT1664HG-26AB2 Micron Technology Inc, MT8VDDT1664HG-26AB2 Datasheet - Page 15
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MT8VDDT1664HG-26AB2
Manufacturer Part Number
MT8VDDT1664HG-26AB2
Description
MODULE SDRAM DDR 128MB 200SODIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT8VDDT3264HG-335G3.pdf
(28 pages)
Specifications of MT8VDDT1664HG-26AB2
Memory Type
DDR SDRAM
Memory Size
128MB
Speed
266MT/s
Package / Case
200-SODIMM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 14: I
DDR SDRAM component values only
Notes: 1–5, 8, 10, 12, 47; notes appear on pages 18–21; 0°C
pdf: 09005aef8092973f, source: 09005aef80921669
DD8C16_32_64x64HG.fm - Rev. B 9/04 EN
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge;
t
once per clock cyle; Address and control inputs changing once
every two clock cycles
OPERATING CURRENT: One device bank; Active -Read Precharge;
Burst = 4;
control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
idle; Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
t
once per clock cycle. V
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge;
andDQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
device bank active; Address and control inputs changing once per
clock cycle;
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once per
clock cycle;
twice per clock cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE
OPERATING CURRENT: Four device bank interleaving READs (BL = 4)
with auto precharge,
control inputs change only during Active READ or WRITE
commands
RC =
CK MIN; CKE = HIGH; Address and other control inputs changing
t
RC (MIN);
t
RC =
t
t
CK =
CK =
t
RC (MIN);
t
DD
CK =
t
t
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs changing
Specifications and Conditions – 512MB
t
t
IN
RC =
CK (MIN); DQ, DM and DQS inputs changing
t
= V
RC =
t
CK =
t
CK =
t
t
REF
CK =
RC (MIN);
OUT
t
RAS (MAX);
t
0.2V
for DQ, DQS, and DM
t
CK (MIN); CKE = (LOW)
CK (MIN); I
= 0mA
t
CK (MIN); CKE = LOW
t
CK =
t
OUT
CK =
t
CK (MIN); Address and
t
t
REFC =
REFC = 7.8125µs
= 0mA; Address and
t
CK (MIN); DQ, DM
t
RFC (MIN)
t
15
CK =
T
A
128MB, 256MB, 512MB (x64, SR)
+70°C; V
I
I
I
I
I
I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
I
DD4W
SYM
I
I
DD3N
I
DD5A
I
I
DD2P
DD3P
DD4R
DD2F
DD0
DD1
DD5
DD6
DD7
DD
= V
1,040
1,280
1,320
1,400
2,320
3,240
DD
-335
360
280
400
40
80
40
200-PIN DDR SODIMM
Q = +2.5V ±0.2V
1,040
1,280
1,320
1,240
2,320
3,200
MAX
-262
360
280
400
40
80
40
©2004 Micron Technology, Inc. All rights reserved.
-26A/
1,160
1,160
1,080
2,240
2,800
-265
920
320
240
360
40
80
40
UNITS NOTES
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
21, 28,
21, 28,
20, 41
20, 41
20, 41
20, 41
24, 43
24, 43
20, 42
43
44
43
20
9