MT9VDDF6472Y-335D3 Micron Technology Inc, MT9VDDF6472Y-335D3 Datasheet - Page 11

• Manufacturer Part Number: MT9VDDF6472Y-335D3
• Description: MODULE SDRAM DDR 512MB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDF6472Y-335D3

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.575A
• Number Of Elements: 9
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10:
PDF: 09005aef8082c948/Source: 09005aef807d56a1
ddf9c32_64x72.fm - Rev. C 10/08 EN
Parameter/Condition
Operating one device bank active-precharge current:
t
Address and control inputs changing once every two clock cycles
Operating one device bank active-read-precharge current: Burst = 4;
t
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Power-
down mode;
Idle standby current: CS# = HIGH; All device banks idle;
= HIGH; Address and other control inputs changing once per clock cycle. VIN =
VREF for DQ, DQS, and DM
Active power-down standby current: One device bank active; Power-
down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank; Active
precharge;
changing twice per clock cycle; Address and other control inputs changing
once per clock cycle
Operating burst read current: Burst = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock cycle;
t
Operating burst write current: Burst = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock cycle;
t
Auto refresh burst current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving
READs; (burst = 4) with auto precharge,
Address and control inputs change only during active READ or WRITE
commands
CK =
RC =
CK =
CK =
t
t
t
t
RC (MIN);
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
CK (MIN); IOUT = 0mA
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
t
RC =
t
t
I
Values are for MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
CK =
CK =
DD
t
CK =
t
RAS (MAX);
Specifications and Conditions – 256MB (All Other Die Revisions)
t
CK (MIN); CKE = (LOW)
t
CK (MIN); CKE = LOW
t
CK (MIN); IOUT = 0mA; Address and control inputs
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs
t
RC =
256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
t
RC (MIN);
t
t
RFC =
RFC = 7.8125µs
t
t
CK =
CK =
t
RC =
11
t
t
RFC (MIN)
t
CK (MIN); CKE
CK (MIN);
t
RC (MIN);
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol -40B
I
I
I
I
I
I
I
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
DD
4W
3N
5A
2P
3P
4R
2F
0
1
5
6
7
1,215 1,125 1,125 1,080
1,530 1,530 1,440 1,305
1,800 1,575 1,350 1,350
1,755 1,575 1,350 1,350
2,340 2,295 2,115 2,115/
4,230 3,690 3,150 3,150/
540
360
630
Electrical Specifications
36
54
36
©2002 Micron Technology, Inc. All rights reserved.
-335
450
270
540
36
54
36
-262
405
225
450
36
54
36
-26A/
2,205
3,285
-265 Units
225/
405
270
450
36
54
36
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA