MT9VDDT3272PHG-265G2 Micron Technology Inc, MT9VDDT3272PHG-265G2 Datasheet - Page 11
![MODULE SDRAM DDR 256MB 200SODIMM](/photos/7/83/78349/mfg_mt_sodimm_series_sml.jpg)
MT9VDDT3272PHG-265G2
Manufacturer Part Number
MT9VDDT3272PHG-265G2
Description
MODULE SDRAM DDR 256MB 200SODIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT9VDDT1672PHG-335D2.pdf
(33 pages)
Specifications of MT9VDDT3272PHG-265G2
Memory Type
DDR SDRAM
Memory Size
256MB
Speed
266MT/s
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
72b
Organization
32Mx72
Total Density
256MByte
Chip Density
256Mb
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.35A
Number Of Elements
9
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Commands
Operation Truth Table, provide a general reference of
available commands. For a more detailed description
Table 8:
CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved
NOTE:
Table 9:
Used to mask write data; provided coincident with the corresponding data
pdf: 09005aef808ffe58, source: 09005aef808ffdc7
DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN
NAME (FUNCTION)
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select device bank and activate row)
READ (Select device bank and column, and start READ burst)
WRITE (Select device bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in device bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable
Write Inhibit
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A11(128MB), A0–A12 (256MB, 512MB), or A0–A13 (1GB) provide row
3. BA0–BA1 provide device bank address; A0–A9 (128MB, 256MB) or A0–A9, A11 (512MB, 1GB) provide column address;
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0–
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don’t Care" except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;
Table 8, Commands Truth Table, and Table 9, DM
address.
A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
bursts with auto precharge enabled and for WRITE bursts.
BA1 are "Don’t Care."
BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11(128MB), A0–A12
(256MB, 512MB), or A0–A13 (1GB) provide the op-code to be written to the selected mode register.
Commands Truth Table
DM Operation Truth Table
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)
11
of commands and operations, refer to the Micron
128Mb, 256Mb, 512Mb, or 1Gb DDR SDRAM compo-
nent data sheets.
CS#
200-PIN DDR SDRAM SODIMM
H
L
L
L
L
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RAS# CAS#
X
H
H
H
H
L
L
L
L
H
H
H
H
X
L
L
L
L
WE#
X
H
H
H
H
L
L
L
L
©2004 Micron Technology, Inc. All rights reserved.
DM
H
L
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
ADVANCE
Valid
DQS
NOTES
X
6, 7
1
1
2
3
3
4
5
8