MT9VDDT6472Y-265D2 Micron Technology Inc, MT9VDDT6472Y-265D2 Datasheet - Page 14
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MT9VDDT6472Y-265D2
Manufacturer Part Number
MT9VDDT6472Y-265D2
Description
MODULE SDRAM DDR 512MB 184DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT9VDDT6472Y-265D2.pdf
(16 pages)
Specifications of MT9VDDT6472Y-265D2
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
266MT/s
Package / Case
184-DIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184RDIMM
Device Core Size
72b
Organization
64Mx72
Total Density
512MByte
Chip Density
512Mb
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.305A
Number Of Elements
9
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT9VDDT6472Y-265D2
Manufacturer:
ITT
Quantity:
6 965
Serial Presence-Detect
Table 16:
Table 17:
Serial Presence-Detect Data
PDF: 09005aef80e119b2/Source: 09005aef80e11976
DD9C16_32_64x72.fm - Rev. D 1/08 EN
Parameter/Condition
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: I
Input leakage current: V
Output leakage current: V
Standby current: SCL = SDA = V
Power supply current: SCL clock frequency = 100 kHz
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
Clock/data fall time
Clock/data rise time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Serial Presence-Detect EEPROM DC Operating Conditions
Serial Presence-Detect EEPROM AC Operating Conditions
Notes:
OUT
IN
= 3mA
OUT
= GND to V
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
For the latest serial presence-detect data, refer to Micron’s SPD page:
www.micron.com/SPD.
128MB, 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
= GND to V
the falling or rising edge of SDA.
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
DD
- 0.3V; All other inputs = V
DD
DD
14
SS
or V
DD
t
t
Symbol
t
t
WRC) is the time from a valid stop condition of a write
t
HD:DAT
t
SU:DAT
SU:STA
SU:STO
t
t
t
H:STA
t
HIGH
LOW
f
WRC
t
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BUF
SCL
AA
DH
t
t
t
R
F
I
Symbol
V
DDSPD
V
V
V
I
I
I
I
LO
SB
CC
OL
LI
IH
IL
Min
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
–
–
0
–
–
–
V
DDSPD
Min
–1.0
2.3
Serial Presence-Detect
–
–
–
–
–
Max
300
300
400
0.9
50
10
× 0.7
–
–
–
–
–
–
–
–
–
©2003 Micron Technology, Inc. All rights reserved
V
V
DDSPD
DDSPD
Units
kHz
Max
ms
µs
µs
ns
ns
ns
µs
µs
µs
ns
µs
ns
µs
µs
3.6
0.4
2.0
10
10
30
+ 0.5
× 0.3
Notes
Units
1
2
2
3
4
mA
µA
µA
µA
V
V
V
V