MT8HTF12864HY-53ED3 Micron Technology Inc, MT8HTF12864HY-53ED3 Datasheet - Page 12

• Manufacturer Part Number: MT8HTF12864HY-53ED3
• Description: MODULE SDRAM DDR2 1GB 200SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8HTF12864HY-53ED3

• Memory Type: DDR2 SDRAM
• Memory Size: 1GB
• Speed: 533MT/s
• Package / Case: 200-SODIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 13:
PDF: 09005aef80eec96e/Source: 09005aef80eec946
HTF8C32_64_128x64HG.fm - Rev. E 6/08 EN
Parameter/Condition
Operating one bank active-precharge current;
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current; I
CL = CL (I
t
bus inputs are switching; Data pattern is same as I
Precharge power-down current; All device banks idle;
is LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current; All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data
bus inputs are floating
Precharge standby current; All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current; All device banks open;
t
inputs are stable; Data bus inputs are floating
Active standby current; All device banks open;
t
commands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current; All device banks open, continuous burst
writes; BL = 4, CL = CL (I
t
bus inputs are switching; Data bus inputs are switching
Operating burst read current; All device banks open, continuous burst
reads, I
t
commands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current;
t
control and address bus inputs are switching; Data bus inputs are switching
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current; All device banks interleaving
reads, I
t
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching; See I
RC =
RCD =
CK =
RAS =
RP =
RAS =
RFC (I
CK =
t
t
t
t
RP (I
DD
RC (I
CK (I
CK (I
t
t
t
OUT
OUT
RAS MAX (I
RAS MAX (I
RCD (I
) interval; CKE is HIGH, S# is HIGH between valid commands; Other
DD
DD
DD
DD
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address
),
DDR2 I
Values are for the MT47H128M8 DDR2 SDRAM only and are computed from values specified in the
1Gb (128 Meg x 8) component data sheet
); CKE is LOW; Other control and address bus
),
DD
t
t
RAS =
RC =
); CKE is HIGH, S# is HIGH between valid commands; Address
DD
DD
t
t
),
),
CK =
DD
RC (I
t
RAS MIN (I
t
t
DD
RP =
RP =
t
CK =
Specifications and Conditions – 1GB (die revision E)
), AL = 0;
DD
t
CK (I
t
t
),
RP (I
RP (I
t
CK (I
t
RRD =
DD
DD
DD
DD
),
DD
DD
DD
t
); CKE is HIGH, S# is HIGH between valid
CK =
256MB, 512MB, 1GB: (x64, SR) 200-Pin DDR2 SDRAM SODIMM
t
); CKE is HIGH, S# is HIGH between valid
); CKE is HIGH, S# is HIGH between valid
RC =
), AL = 0;
); Refresh the command at every
), AL =
t
RRD (I
t
CK (I
t
RC (I
t
DD
RCD (I
DD
t
),
DD
CK =
),
t
t
DD
RCD =
),
CK =
t
t
DD
RAS =
CK =
t
t
4W
DD
RAS =
CK =
t
CK (I
) - 1 ×
7 conditions for detail
t
CK (I
t
t
t
RCD (I
OUT
CK =
CK (I
t
t
DD
t
CK (I
RAS MAX (I
t
CK =
12
RAS MIN (I
t
DD
),
CK (I
= 0mA; BL = 4,
DD
t
Fast PDN Exit
MR[12] = 0
Slow PDN Exit
MR[12] = 1
DD
),
CK (I
DD
t
),
CK (I
); CKE is
DD
); CKE is
DD
);
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
DD
); CKE
);
),
),
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
6
7
-80E/
-800 -667 -53E -40E Units
1280 1080 1000
1280 1080 1000
1880 1720 1680 1640
2680 2240 2160 2080
Electrical Specifications
720
880
400
400
320
480
56
80
56
©2004 Micron Technology, Inc. All rights reserved.
680
800
320
320
240
440
56
80
56
560
760
320
320
240
360
56
80
56
560
720
280
280
240
320
840
840
56
80
56
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA