MT36HTS51272FY-667A2D3 Micron Technology Inc, MT36HTS51272FY-667A2D3 Datasheet - Page 6
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT36HTS51272FY-667A2D3
Manufacturer Part Number
MT36HTS51272FY-667A2D3
Description
MODULE DDR2 4GB 240FBDIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT36HTS51272FY-53EA2E3.pdf
(35 pages)
Specifications of MT36HTS51272FY-667A2D3
Memory Type
DDR2 SDRAM
Memory Size
4GB
Speed
667MT/s
Package / Case
240-FBDIMM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Introduction
FBDIMM Specification Details
PDF: 09005aef822148b0/source: 09005aef82214898
HTS36C512x72F_2.fm - Rev. A 4/06 EN
1. FBDIMM Design Specification
2. FBDIMM Architecture and Protocol Specification
3. FBDIMM AMB Specification
4. FBDIMM Link Signaling Specification
5. FBDIMM DFx Specification
The JEDEC FBDIMM specification consists of the following sections and can be found at
the JEDEC Web site member’s area.
Each of these sections contains detailed information about the various aspects of
FBDIMM construction, interfaces, and theory of operation. The JEDEC specification is
simply too long and complex to condense into a single data sheet; minimal references
are made throughout this document to give a brief overview. For design guidance and
final specification information, designers must refer to the JEDEC FBDIMM specifica-
tion.
Defines the electrical and mechanical requirements for 240-pin, PC2-4200/PC2-5300,
72-bit wide, fully buffered double data rate synchronous DRAM dual in-line memory
modules (DDR2 SDRAM FBDIMMs). These DDR2 SDRAM FBDIMMs are intended for
use as main memory when installed in systems such as servers and workstations.
PC2-4200/PC2-5300 refers to the DIMM naming convention in which PC2-4200/PC2-
5300 indicates a 240-pin DDR2 DIMM running at 266/333 MHz DDR2 SDRAM clock
speed and offering 4.2/5.3 GB/s bandwidth.
Reference design examples are included which provide an initial basis for FBDIMM
designs. Modifications to these reference designs may be required to meet all system
timing, signal integrity, and thermal requirements for PC2-4200/PC2-5300/ support.
All FBDIMM implementations must use simulations and lab verification to ensure
proper timing requirements and signal integrity in the design.
Describes FBDIMM channel topology, physical signaling, clocking, and data flow.
Core specification for a FBDIMM memory system. This document, along with the
other core specifications, must be treated as a whole. Information critical to an AMB
design appears in the other specifications, with specific cross-references provided.
Defines the high-speed, differential, point-to-point signaling link for FBDIMM, oper-
ating at AMB V
applies to FBDIMM host chips which may operate with a different supply voltage. The
link consists of a transmitter, a receiver, and the interconnect between them. The
transmitter sends serialized bits into a lane and the receiver accepts the electrical sig-
nals of the serialized bits and transforms them into a serialized bit-stream. The first-
generation FBDIMM link is specified for 3.2–4.0 Gb/s and defined for three distinct
bit rates: 3.2 Gb/s and 4.0 Gb/s.
The link utilizes a derived-clock approach and transmitter de-emphasis to compen-
sate for channel loss characteristics. The link definition has the flexibility to accom-
modate future silicon enhancement circuits, such as forwarded clocking or advanced
equalization techniques, to meet future signaling targets.
Defines design for test, design for manufacturing, and design for validation (DFx)
requirements and implementation guidelines for FBDIMM technology.
CC
= 1.5V, provided at the FBDIMM connector. This specification also
240-Pin 4GB DDR2 SDRAM FBDIMM (DR, FB, x72)
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
Introduction
Preliminary