MT9HTF6472Y-667D4 Micron Technology Inc, MT9HTF6472Y-667D4 Datasheet - Page 14

• Manufacturer Part Number: MT9HTF6472Y-667D4
• Description: MODULE DDR2 512MB 240-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9HTF6472Y-667D4

• Memory Type: DDR2 SDRAM
• Memory Size: 512MB
• Speed: 667MT/s
• Package / Case: 240-DIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.575A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Table 16:
Table 17:
PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd
HTF9C32_64_128x72K.fm - Rev. C 9/06 EN
Parameter/Condition
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: I
Input leakage current: V
Output leakage current: V
Standby current:
Power Supply Current, READ: SCL clock frequency = 100 KHz
Power Supply Current, WRITE: SCL clock frequency = 100 KHz
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
Notes:
OUT
IN
= 3mA
OUT
= GND to V
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM
= GND to V
the falling or rising edge of SDA.
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tor, and the EEPROM does not respond to its slave address.
DDSPD
SS
SS
DDSPD
; V
; V
DDSPD
DDSPD
= +1.7V to +3.6V
= +1.7V to +3.6V
14
t
WRC) is the time from a valid stop condition of a write
t
Symbol
Symbol
t
t
t
t
HD:DAT
V
HD:STA
SU:DAT
SU:STO
SU:STA
t
t
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
HIGH
DDSPD
I
LOW
f
WRC
V
I
t
t
BUF
V
V
I
CC
SCL
I
AA
DH
CC
I
t
LO
t
SB
t
OL
LI
R
IH
F
IL
I
W
R
Register and PLL Specifications
V
DDSPD
Min
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
0
Min
–0.6
0.10
0.05
1.7
1.6
0.4
2
–
× 0.7
Max
300
400
0.3
0.9
50
10
©2005 Micron Technology, Inc. All rights reserved.
V
V
DDSPD
DDSPD
Max
3.6
0.4
3
3
4
1
3
Units
KHz
+ 0.5
× 0.3
ms
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
Units
Notes
mA
mA
µA
µA
µA
V
V
V
V
1
2
2
3
4