NHD-C160100DIZ-FSW-FBW Newhaven Display, NHD-C160100DIZ-FSW-FBW Datasheet - Page 6
![LCD COG GRAPH 160X100 WH TRANSFL](/photos/7/92/79244/nhd-c160100diz-fsw-fbw_sml.jpg)
NHD-C160100DIZ-FSW-FBW
Manufacturer Part Number
NHD-C160100DIZ-FSW-FBW
Description
LCD COG GRAPH 160X100 WH TRANSFL
Manufacturer
Newhaven Display
Series
NHD-C160100DIZ-Fr
Datasheet
1.NHD-C160100DIZ-FSW-FBW.pdf
(15 pages)
Specifications of NHD-C160100DIZ-FSW-FBW
Display Type
LCD
Display Mode
Transflective
Viewing Area
46.2mm L x 33.89mm W
Backlight
LED - White
Dot Size
0.23mm W x 0.23mm H
Dot Pitch
0.25mm x 0.25mm
Dot Pixels
160 x 100
Interface
Serial
Pixel Density
160 x 100
Fluid Type
FSTN Positive
Module Size (w X H X T)
49.2 mm x 47.6 mm x 4 mm
Viewing Area (w X H)
46.2 mm x 33.89 mm
Backlighting
Side LED White
Operating Temperature Range
- 20 C to + 70 C
Attached Touch Screen
No
Product
COG LCD Module
Style
COG LCD Module
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
I2C Interface:
I2C interface requires 2 lines, Serial Data and Serial Clock. Both lines must be connected to the positive supply via a
pull-up resistor. Data transfer may be initiated only when the bus is not busy.
Bit transfer:
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH
period of the clock pulse, changes in the data line at this time will be interpreted as a control signal.
Start and Stop conditions:
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the
clock is HIGH is define as the START condition. A LOW-to-HIGH transition of the data line while the clock is HIGH is
defined as the STOP condition.
Acknowledge:
Each byte of eight bits is followed by an acknowledge bit. The ACK bit is a HIGH signal put on the bus by the
transmitter, during which time the master generates an extra ACK related clock pulse. The LCD generates an ACK after
the reception of each byte. The LCD will pull-down the SDA line during the ACK clock pulse, so that the SDA line is
stable LOW during the HIGH period of the ACK clock pulse.
Slave Address = 0x3F
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